The TPS3702-Q1 is an integrated overvoltage and undervoltage window voltage detector in a small SOT-6 package. This highly accurate voltage detector is an excellent choice for systems that operate on low-voltage supply rails and have narrow margin supply tolerances. Low threshold hysteresis options of 0.55% and 1.0% prevent false reset signals when the monitored voltage supply is in the normal range of operation. Internal glitch immunity and noise filters further eliminate false resets resulting from erroneous signals.
The TPS3702-Q1 does not require any external resistors for setting overvoltage and undervoltage reset thresholds, which further increases overall accuracy and reduces solution size and cost. The SET pin is used to select between the two available threshold voltages designed into each device. A separate SENSE input pin and VDD pin allow for the redundancy sought by safety-critical and high-reliability systems. This device also features independent reset outputs for the OV and UV pins; as a result of the open-drain configuration, UV and OV can be tied together.
This device has a low typical quiescent current specification of 7µA . The TPS3702-Q1 is designed for automotive applications and is qualified for AEC-Q100 Grade 1.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | UV | O | Active-low, open-drain undervoltage output. This pin goes low when the SENSE voltage falls below the internally set undervoltage threshold (VIT–). See the timing diagram in Figure 5-1 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up voltage. |
2 | GND | — | Ground |
3 | SENSE | I | Input for the monitored supply voltage rail. When the SENSE voltage goes below the undervoltage threshold, the UV pin is driven low. When the SENSE voltage goes above the overvoltage threshold, the OV pin is driven low. |
4 | SET | I | Use this pin to configure the threshold voltages. Refer to Table 8-1 for the desired configuration. |
5 | VDD | I | Supply voltage input pin. To
power the device, connect a voltage supply (within the range of 2V
and 18V) to VDD. Good analog design practice is to place a 0.1μF ceramic capacitor close to this pin. |
6 | OV | O | Active-low, open-drain overvoltage output. This pin goes low when the SENSE voltage rises above the internally set overvoltage threshold (VIT+). See the timing diagram in Figure 5-1 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up voltage. |