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  • TPS3851 Precision Voltage Supervisor with Integrated Watchdog Timer

    • SBVS300A November   2016  – September 2021 TPS3851

      PRODUCTION DATA  

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  • TPS3851 Precision Voltage Supervisor with Integrated Watchdog Timer
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 RESET
      2. 7.3.2 Manual Reset MR
      3. 7.3.3 UV Fault Detection
      4. 7.3.4 Watchdog Mode
        1. 7.3.4.1 CWD
        2. 7.3.4.2 Watchdog Input WDI
        3. 7.3.4.3 Watchdog Output WDO
        4. 7.3.4.4 SET1
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDD is Below VPOR ( VDD < VPOR)
      2. 7.4.2 Above Power-On-Reset, But Less Than VDD(min) (VPOR ≤ VDD < VDD(min))
      3. 7.4.3 Normal Operation (VDD ≥ VDD(min))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CWD Functionality
        1. 8.1.1.1 Factory-Programmed Timing Options
        2. 8.1.1.2 Adjustable Capacitor Timing
      2. 8.1.2 Overdrive Voltage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Monitoring the 1.8-V Rail
        2. 8.2.2.2 Calculating RESET and WDO Pullup Resistor
        3. 8.2.2.3 Setting the Watchdog
        4. 8.2.2.4 Watchdog Disabled During Initialization Period
      3. 8.2.3 Glitch Immunity
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • DRB|8
    • MPDS118K
Thermal pad, mechanical data (Package|Pins)
  • DRB|8
    • QFND058N
Orderable Information
  • sbvs300a_oa
  • sbvs300a_pm
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DATA SHEET

TPS3851 Precision Voltage Supervisor with Integrated Watchdog Timer

1 Features

  • Input voltage range: VDD = 1.6 V to 6.5 V
  • 0.8% Voltage threshold accuracy
  • Low quiescent current: IDD = 10 µA (typical)
  • User-programmable watchdog timeout
  • Open-drain outputs
  • Precision undervoltage monitoring:
    • Supports common rails from 1.8 V to 5.0 V
    • 4% and 7% Undervoltage thresholds available
    • 0.5% Hysteresis
  • Watchdog disable feature
  • Factory-programmed precision watchdog and reset timers
  • Manual reset input (MR)
  • Available in a small 3-mm × 3-mm, 8-Pin VSON package
  • Junction operating temperature range:
    –40°C to +125°C

2 Applications

  • WLAN/Wi-Fi access point
  • Wireless security camera
  • IP network camera
  • String inverter
  • Blood pressure monitor
  • Electricity meter

3 Description

The TPS3851 combines a precision voltage supervisor with a programmable watchdog timer. The TPS3851 comparator achieves a 0.8% accuracy
(–40°C to +125°C) for the undervoltage (VITN) threshold on the VDD pin. The TPS3851 also includes accurate hysteresis on the undervoltage threshold making the device ideal for use with tight tolerance systems. The supervisor RESET delay features a 15% accuracy, high-precision delay timing.

The TPS3851 includes a programmable watchdog timer for a wide variety of applications. The dedicated watchdog output (WDO) enables increased resolution to help determine the nature of fault conditions. The watchdog timeouts can be programmed either by an external capacitor, or by factory-programmed default delay settings. The watchdog can be disabled via logic pins to avoid undesired watchdog timeouts during the development process.

TPS3851 is available in a small 3.00-mm × 3.00-mm, 8-pin VSON package.

Device Information
PART NUMBER PACKAGE (1) BODY SIZE (NOM)
TPS3851 VSON (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-E15FD24A-2AE7-44D6-A29A-08D5C581CC30-low.gifFully Integrated Microcontroller Supervisory Circuit
GUID-98A16D2E-6E03-43AB-9647-9F017EDE04D7-low.gifUndervoltage Threshold (VITN) Accuracy vs Temperature

4 Revision History

Changes from Revision * (November 2016) to Revision A (September 2021)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Removed "±15% Accurate WDT and RST Delays"Go
  • Added "on the VDD pin"Go
  • Changed VESD values to ±4000 V and ±1000 VGo
  • Changed ICWD min and max spec Go
  • Changed VCWD min and max spec Go
  • Added a footnote to for tINIT Go
  • Updated tWDU min and max multipliers from 0.85 and 1.15 to 0.905 and 1.095 respectivelyGo
  • Updated tWDU min and max values for all capacitorsGo
  • Updated equation 6 and 7 to replace 0.85 and 1.15 with 0.905 and 1.095 respectivelyGo

5 Pin Configuration and Functions

Figure 5-1 DRB Package: TPS3851
3-mm × 3-mm VSON-8
Top View
Table 5-1 Pin Functions
NAME NO. I/O DESCRIPTION
CWD 2 I Programmable watchdog timeout input. The watchdog timeout is set by connecting a capacitor between this pin and ground. Connecting via a 10-kΩ resistor to VDD or leaving unconnected further enables the selection of the preset watchdog timeouts; see the CWD Functionality section.
The TPS3851 determines the watchdog timeout using either Equation 1 or Equation 2 with standard or extended timing, respectively.
GND 4 — Ground pin
MR 3 I Manual reset pin. A logical low on this pin issues a RESET. This pin is internally pulled up to VDD. RESET remains low for a fixed reset delay (tRST) time after MR is deasserted (high).
RESET 8 O Reset output. Connect RESET using a 1-kΩ to 100-kΩ resistor to the correct pullup voltage rail (VPU). RESET goes low when VDD goes below the undervoltage threshold (VITN). When VDD is within the normal operating range, the RESET timeout-counter starts. At completion, RESET goes high. During startup, the state of RESET is undefined below the specified power-on-reset (POR) voltage (VPOR). Above POR, RESET goes low and remains low until the monitored voltage is within the correct operating range (above VITN+VHYST) and the RESET timeout is complete.
SET1 5 I Logic input. Grounding the SET1 pin disables the watchdog timer. SET1 and CWD select the watchdog timeouts; see the SET1 section.
VDD 1 I Supply voltage pin. For noisy systems, connecting a 0.1-μF bypass capacitor is recommended.
WDI 6 I Watchdog input. A falling edge must occur at WDI before the timeout (tWD) expires.
When the watchdog is not in use, the SET1 pin can be used to disable the watchdog. WDI is ignored when RESET or WDO are low (asserted) and when the watchdog is disabled. If the watchdog is disabled, WDI cannot be left unconnected and must be driven to either VDD or GND.
WDO 7 O Watchdog output. Connect WDO with a 1-kΩ to 100-kΩ resistor to the correct pullup voltage rail (VPU). WDO goes low (asserts) when a watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout occurs, WDO goes low (asserts) for the set RESET timeout delay (tRST). When RESET goes low, WDO is in a high-impedance state.
Thermal pad — Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

 
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