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TPS51206 2-A Peak Sink / Source DDR Termination Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and DDR4
SLUSAH1E
MAY 2011 – July 2018
TPS51206
PRODUCTION DATA.
CONTENTS
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TPS51206 2-A Peak Sink / Source DDR Termination Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and DDR4
1
Features
2
Applications
3
Description
Device Images
Simplified Application
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
VTT Sink and Source Regulator
7.3.2
VTTREF
7.3.3
VDD Undervoltage Lockout Protection
7.3.4
VTT Current Limit
7.3.5
Overtemperature Protection
7.3.6
Power On and Off Sequence
7.4
Device Functional Modes
7.4.1
Power State Control
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
VLDOIN = VDDQ Configuration
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
VDD Capacitor
8.2.1.2.2
VLDOIN Capacitor
8.2.1.2.3
VTTREF Capacitor
8.2.1.2.4
VTT Capacitor
8.2.1.2.5
VTTSNS Connection
8.2.1.2.6
VDDQSNS Connection
8.2.1.3
Application Curves
8.2.2
VLDOIN Separated from VDDQ Configuration
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
10.3
Thermal Considerations
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.2
Receiving Notification of Documentation Updates
11.3
Community Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
DSQ|10
MPDS335B
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slusah1e_oa
slusah1e_pm
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DATA SHEET
TPS51206 2-A Peak Sink / Source DDR Termination Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and DDR4
1
Features
Supply Input Voltage: Supports 3.3-V Rail and 5-V Rail
VLDOIN Input Voltage Range: VTT+0.4 V to 3.5 V
VTT Termination Regulator
Output Voltage Range: 0.5 V to 0.9 V
2-A Peak Sink and Source Current
Requires Only 10-μF MLCC Output Capacitor
±20 mV Accuracy
VTTREF Buffered Reference
VDDQ/2 ± 1% Accuracy
10-mA Sink and Source Current
Supports High-Z in S3 and Soft-Stop in S4 and S5 with S3 and S5 Inputs
Overtemperature Protection
10-Pin, 2 mm × 2 mm SON (DSQ) Package
2
Applications
DDR2, DDR3, DDR3L, and DDR4 Memory Power Supplies
SSTL_18, SSTL_15, SSTL_135 and HSTL Termination
Telecom and Datacom, GSM Base Station, LCD-TV and PDP-TV, Copier and Printer, Set-top Box