The TPS51206 device is a sink and source double date rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low-cost, low-external component count systems where space is a key consideration. The device maintains fast transient response and only requires 1 × 10-µF of ceramic output capacitance. The device supports a remote sensing function and all power requirements for DDR2, DDR3 and Low-Power DDR3 (DDR3L), and DDR4 VTT bus. The VTT current capability is ±2-A peak. The device supports all of the DDR power states, putting VTT to High-Z in S3 state (suspend to RAM) and discharging VTT and VTTREF in S4 or S5 state (suspend to disk).
The TPS51206 device is available in 10-Pin, 2 mm × 2 mm SON (DSQ) PowerPAD™ package and specified from –40°C to 105°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS51206 | WSON (10) | 2.00 mm × 2.00 mm |
Changes from D Revision (March 2018) to E Revision
Changes from C Revision (August 2016) to D Revision
Changes from B Revision (December 2014) to C Revision
Changes from A Revision (October 2013) to B Revision
Changes from * Revision (MAY 2011) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
GND | 8 | – | Signal ground |
PGND | 4 | – | Power GND for VTT LDO |
S3 | 7 | I | S3 signal input |
S5 | 9 | I | S5 signal input |
VDD | 10 | I | Device power supply input (3.3 V or 5 V) |
VDDQSNS | 1 | I | VDDQ sense input, reference input for VTTREF |
VLDOIN | 2 | I | Power supply input for VTT/ VTTREF |
VTT | 3 | O | Power output for VTT LDO, need to connect 10-μF or greater MLCC for stability. No maximum limit for VTT output capacitance. |
VTTREF | 6 | O | VTTREF buffered reference output. Connect to MLCC between 0.22-µF and 1-µF for stability. The VTTREF pin can not be open. |
VTTSNS | 5 | I | VTT LDO voltage sense input |
Thermal Pad | — | Solder to the ground plane for increased thermal performance. |