TPS51604 Synchronous Buck FET Driver for High-Frequency CPU Core Power
- SLUSBA6B December 2012 – October 2015 TPS51604
  
  PRODUCTION DATA.

Full reading width

DATA SHEET

TPS51604 Synchronous Buck FET Driver for High-Frequency CPU Core Power

1 Features

Reduced Dead-Time Drive Circuit for Optimized CCM
Automatic Zero Crossing Detection for Optimized DCM Efficiency
Multiple Low-Power Modes for Optimized Light-Load Efficiency
Optimized Signal Path Delays for High-Frequency Operation
Integrated BST Switch Drive Strength Optimized for Ultrabook FETs
Optimized for 5-V FET Drive
Conversion Input Voltage Range (V_IN): 4.5 to 28 V
2-mm × 2-mm, 8-Pin, WSON Thermal Pad Package

2 Applications

Tablets Using High-Frequency CPUs With the Following Power Input:
- Adapter
- Battery
- NVDC
- 5-V or 12-V Rails

3 Description

The TPS51604 drivers are optimized for high-frequency CPU V_CORE applications. Advanced features such as reduced dead-time drive and auto zero crossing are used to optimize efficiency over the entire load range.

The SKIP pin provides the option of CCM operation to support controlled management of the output voltage. In addition, the TPS51604 supports two low-power modes. With the PWM input in tri-state, quiescent current is reduced to 130 µA, with immediate response. When SKIP is held at tri-state, the current is reduced to 8 µA (typically 20 µs is required to resume switching). Paired with the appropriate TI controller, the drivers deliver an exceptionally high performance power supply system.

The TPS51604 device is packaged in a space saving, thermally-enhanced 8-pin, 2-mm x 2-mm WSON package and operates from –40°C to 105°C.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS51604	WSON (8)	2.00 mm × 2.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

4 Revision History

Changes from A Revision (August 2013) to B Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

5 Pin Configuration and Functions

DSG Package

8-Pin WSON

Top View

Pin Functions

PIN		I/O⁽¹⁾	DESCRIPTION
NAME	NO.	I/O⁽¹⁾	DESCRIPTION
BST	1	I	High-side N-channel FET bootstrap voltage input; power supply for high-side driver
DRVH	8	O	High-side N-channel gate drive output
DRVL	5	O	Synchronous low-side N-channel gate drive output
GND	6	G	Synchronous low-side N-channel gate drive return and device reference
PWM	2	I	PWM input. A tri-state voltage on this pin turns off both the high-side (DRVH) and low-side drivers (DRVL)
SKIP	3	I	When SKIP is LO, the zero crossing comparator is active. The power chain enters discontinuous conduction mode when the inductor current reaches zero. When SKIP is HI, the zero crossing comparator is disabled, and the driver outputs follow the PWM input. A tri-state voltage on SKIP puts the driver into a very-low power state.
SW	7	I/O	High-side N-channel gate drive return. Also, zero-crossing sense input
VDD	4	I	5-V power supply input; decouple to GND with a ceramic capacitor with a value of 1 µF or greater
Thermal Pad		G	Tie to system GND plane with multiple vias

(1) I = Input, O = Output, G = Ground

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾ ⁽²⁾

over operating free-air temperature (unless otherwise noted)

		MIN	MAX	UNIT
Input voltage	VDD	–0.3	6	V
Input voltage	PWM, SKIP	–0.3	6	V
Output voltage	BST	–0.3	35	V
	BST (transient <20 ns)	–0.3	38
	BST to SW; DRVH to SW	–0.3	6
	SW	–2	30
	DRVH, SW (transient <20 ns)	–5	38
	DRVL	–0.3	6
Ground pins	GND to PAD	–0.3	0.3	V
Operating junction temperature, T_J		–40	125	°C
Storage temperature range, T_stg		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per AEC Q100-011	±750	V

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
Input voltage	VDD	4.5	5	5.5	V
Input voltage	PWM, SKIP	–0.1		5.5	V
Output voltage	BST	–0.1		34	V
	BST to SW; DRVH to SW	–0.1		5.5
	SW	–1		28
	DRVL	–0.1		5.5
Ground pins	GND to PAD	–0.1		0.1	V
Operating junction temperature, T_J		–40		105	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS51604	UNIT
		WSON (DSG)
		8 PINS
R_θJA	Junction-to-ambient thermal resistance	63.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	74.1	°C/W
R_θJB	Junction-to-board thermal resistance	34.3	°C/W
ψ_JT	Junction-to-top characterization parameter	2.0	°C/W
ψ_JB	Junction-to-board characterization parameter	34.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	11.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

These specifications apply for –40°C ≤ T_J ≤ 105°C, and V_VDD = 5 V unless otherwise specified.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VDD INPUT SUPPLY
I_CC	Supply current (operating)	V_SKIP = V_VDD or V_SKIP = 0 V, PWM = High		160	600	µA
		V_SKIP = V_VDD or V_SKIP = 0 V, PWM = Low		250
		V_SKIP = V_VDD or V_SKIP = 0 V, PWM = Float		130
		V_SKIP = Float		8
VDD UNDERVOLTAGE LOCKOUT (UVLO)
V_UVLO	UVLO threshold	Rising threshold			4.15	V
V_UVLO	UVLO threshold	Falling threshold	3.7			V
V_UVHYS	UVLO hysteresis			0.2		V
PWM AND SKIP I/O SPECIFICATIONS
R_I	Input impedance	Pullup to VDD		1.7		MΩ
R_I	Input impedance	Pulldown (to GND)		800		kΩ
V_IL	Low-level input voltage				0.6	V
V_IH	High-level input voltage		2.65			V
V_IHH	Hysteresis			0.2		V
V_TS	Tri-state voltage		1.3		2.0	V
t_THOLD(off1)	Tri-state activation time (falling) PWM			60		ns
t_THOLD(off2)	Tri-state activation time (rising) PWM			60		ns
t_TSKF	Tri-state activation time (falling) SKIP			1		µs
t_TSKR	Tri-state activation time (rising) SKIP			1		µs
t_3RD(PWM)	Tri-state exit time PWM				100	ns
t_3RD(SKIP)	Tri-state exit time SKIP				50	µs
HIGH-SIDE GATE DRIVER (DRVH)
t_R(DRVH)	Rise time	DRVH rising, C_DRVH = 3.3 nF; 20% to 80%		30		ns
t_RPD(DRVH)	Rise time propogation delay	C_DRVH = 3.3 nF		40		ns
R_SRC	Source resistance	Source resistance, (V_BST– V_SW) = 5 V, high state, (V_BST – V_DRVH) = 0.1 V		4	8	Ω
t_F(DRVH)	Fall time	DRVH falling, C_DRVH = 3.3 nF		8		ns
t_FPD(DRVH)	Fall-time propagation delay	C_DRVH = 3.3 nF		25		ns
R_SNK	Sink resistance	Sink resistance, (V_BST – V_SW) forced to 5 V, low state (V_DRVH – V_SW) = 0.1 V		0.5	1.6	Ω
R_DRVH	DRVH to SW resistance⁽¹⁾			100		kΩ
LOW-SIDE GATE DRIVER (DRVL)
t_R(DRVL)	Rise time	DRVL rising, C_DRVL = 3.3 nF; 20% to 80%		15		ns
t_RPD(DRVL)	Rise time propagation delay	C_DRVL = 3.3 nF		35		ns
R_SRC	Source resistance	Source resistance, (V_VDD–GND) = 5 V, high state, (V_VDD – V_DRVL) = 0.1 V		1.5	3	Ω
t_F(DRVL)	Fall time	DRVL falling, C_DRVL = 3.3 nF		10		ns
t_FPD(DRVL)	Fall-time propagation delay	C_DRVL= 3.3 nF		15		ns
R_SNK	Sink resistance	Sink resistance, (V_VDD– GND) = 5 V, low state, (V_DRVL – GND) = 0.1 V		0.4	1.6	Ω
R_DRVL	DRVL to GND resistance⁽¹⁾			100		kΩ
GATE DRIVER DEAD-TIME
t_R(DT)	Rising edge		0	20	35	ns
t_F(DT)	Falling edge		0	10	25	ns
ZERO CROSSING COMPARATOR
V_ZX	Zero crossing offset	SW voltage rising	–2.25	0	2.00	mV
BOOTSTRAP SWITCH
V_FBST	Forward voltage	I_F = 10 mA		120	240	mV
I_RLEAK	Reverse leakage	(V_BST – V_VDD) = 25 V			2	µA
R_DS(on)	On-resistance			12	24	Ω

(1) Specified by design. Not production tested.

6.6 Typical Characteristics

Figure 1. PWM High to DRVL Low

Figure 3. DRVL Low to DRVH High

Figure 5. PWM Low to Tri-State

Figure 7. SKIP Mode Entry

Figure 9. Very-Low-Power Mode Entry

V_IN = 8 V

Figure 11. SW Node-Ringing

Figure 2. PWM Low to DRVH Low

Figure 4. DRVH Low to DRVL High

Figure 6. PWM Tri-State to Low

Figure 8. SKIP Mode Exit

Figure 10. Very-Low-Power Mode Exit

V_IN = 20 V

Figure 12. SW Node-Ringing

6.7 Typical Power Block MOSFET Characteristics

Power block MOSFET: CSD87330, Inductor: 0.22 µF, 1.1-mΩ DCR

FCCM	V_OUT = 1.8 V
V_IN = 7.4 V	f_SW = 800 kHz

Figure 13. Efficiency vs Output Current, FCCM

Skip Mode	V_OUT = 1.8 V
V_IN = 7.4 V	f_SW = 800 kHz

Figure 14. Efficiency vs Output Current, SKIP Mode

7 Detailed Description

7.1 Overview

The TPS51604 device is a synchronous-buck MOSFET driver designed to drive both high-side and low-side MOSFETs. It allows high-frequency operation with current driving capability matched to the application. The integrated boost switch is internal. The TPS51604 device employs dead-time reduction control and shoot-through protection, which helps avoid simultaneous conduction of high-side and low-side MOSFETs. Also, the drivers improve light-load efficiency with integrated DCM-mode operation using adaptive crossing detection. Typical applications yield a steady-state duty cycle of 60% or less. For high steady-state duty cycle applications, including a small external Schottky diode may help to ensure sufficient charging of the bootstrap capacitor.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 UVLO Protection

The UVLO comparator evaluates the VDD voltage level. As V_VDD rises, both DRVH and DRVL hold actively low at all times until V_VDD reaches the higher UVLO threshold (V_{UVLO_H}). Then, the driver becomes operational and responds to PWM and SKIP commands. If VDD falls below the lower UVLO threshold (V_{UVLO_L} = V_{UVLO_H} – Hysteresis), the device disables the driver and drives the outputs of DRVH and DRVL actively low. Figure 15 shows this function.

CAUTION

Do not start the driver in the very low power mode (SKIP = Tri-state).

Figure 15. UVLO Operation

7.3.2 PWM Pin

The PWM pin incorporates an input tri-state function. The device forces the gate driver outputs to low when PWM is driven into the tri-state window and the driver enters a low power state with zero exit latency. The pin incorporates a weak pullup to maintain the voltage within the tri-state window during low-power modes. Operation into and out of a tri-state condition follows the timing diagram outlined in Figure 16.

When VDD reaches the UVLO_H level, a tri-state voltage range (window) is set for the PWM input voltage. The window is defined as the PWM voltage range between PWM logic high (V_IH) and logic low (V_IL) thresholds. The device sets high-level input voltage and low-level input voltage threshold levels to accommodate both 3.3-V (typical) and 5-V (typical) PWM drive signals.

When the PWM exits the tri-state condition, the driver enters CCM for a period of 4 µs, regardless of the state of the SKIP pin. Typical operation requires this time period in order for the auto-zero comparator to resume.

Figure 16. PWM Tri-State Timing Diagram

7.3.3 SKIP Pin

The SKIP pin incorporates the input tri-state buffer as PWM. The function is somewhat different. When SKIP is low, the zero crossing (ZX) detection comparator is enabled, and DCM mode operation occurs if the load current is less than the critical current. When SKIP is high, the ZX comparator disables, and the converter enters FCCM mode. When the SKIP pin is in a tri-state condition, typical operation forces the gate driver outputs low and the driver enters a very-low-power state. In the low-power state, the UVLO comparator remains off to reduce quiescent current. When the SKIP pin voltage is pulled either low or high, the driver wakes up and is able to accept PWM pulses in less than 50 µs.

Table 1 shows the logic functions of UVLO, PWM, SKIP, DRVH, and DRVL.

Table 1. Logic Functions of the TPS51604

UVLO	PWM	SKIP	DRVL	DRVH	MODE
Active	—	—	Low	Low	Disabled
Inactive	Low	Low	High⁽¹⁾	Low	DCM⁽¹⁾
Inactive	Low	High	High	Low	FCCM
Inactive	High	H or L	Low	High
Inactive	Tri-state	H or L	Low	Low	Low power
Inactive	—	Tri-state	Low	Low	Very-low power

(1) Until zero crossing protection occurs.

7.3.3.1 Zero Crossing (ZX) Operation

The zero crossing comparator is adaptive for improved accuracy. As the output current decreases from a heavy load condition, the inductor current also reduces and eventually arrives at a valley, where it touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The SW pin detects the zero-current condition. When this zero inductor current condition occurs, the ZX comparator turns off the rectifying MOSFET.

7.3.4 Adaptive Dead-Time Control and Shoot-Through Protection

The driver utilizes an anti-shoot-through and adaptive dead-time control to minimize low-side body diode conduction time and maintain high efficiency. When the PWM input voltage becomes high, the low-side MOSFET gate voltage begins to fall after a propagation delay. At the same time, DRVL voltage is sensed, and high-side driving voltage starts to increase after DRVL voltage is lower than a proper threshold.

Figure 17. Rise and Fall Timing and Propagation Delay Definitions

Typical operation manages to near zero the dead-time between the low-side gate turn-off to high-side gate voltage turn-on, and high-side gate turn-off to low-side gate turn-on, in order to avoid simultaneous conduction of both MOSFETs, as well as to reduce body diode conduction and recovery losses. This operation also reduces ringing on the leading edge of the SW waveform.

Figure 18. Dead-Time Definitions

7.3.5 Integrated Boost-Switch

To maintain a BST-SW voltage close to VDD (to get lower conduction losses on the high-side FET), the conventional diode between the VDD pin and BST pin is replaced by a FET, which is gated by the DRVL signal.

7.4 Device Functional Modes

The TPS51604 device operates in CCM mode when the SKIP pin is high, and it enters DCM mode when the SKIP pin is low. When both the SKIP pin and the PWM pin are in a tri-state condition, it forces the gate driver outputs low and the driver enters a very-low-power state.