TPS53317A 6-A Output, D-CAP+ Mode, Synchronous Step-Down, Integrated-FET Converter for DDR Memory Termination

1 Features

TI-Proprietary Integrated MOSFET and Packaging Technology
Supports DDR Memory Termination with up to 6-A Continuous Output Source or Sink Current
External Tracking
Minimum External Components Count
0.9-V to 6-V Conversion Voltage
D-CAP+™ Mode Architecture
Supports All MLCC Output Capacitors and SP/POSCAP
Selectable SKIP Mode or Forced CCM
Optimized Efficiency at Light and Heavy Loads
Selectable 600-kHz or 1-MHz Switching Frequency
Selectable Overcurrent Limit (OCL)
Overvoltage, Over-Temperature and Hiccup Undervoltage Protection
Adjustable Output Voltage from 0.45 V to 2 V
3.5 mm × 4 mm, 20-Pin, VQFN Package

2 Applications

Memory Termination Regulator for DDR, DDR2, DDR3, DDR3L, and DDR4
VTT Termination
Low-Voltage Applications for 0.9-V to 6-V Input Rails

3 Description

The TPS53317A device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ V_DDQ with both sink and source capability. The TPS53317A device employs D-CAP+ mode operation that provides ease of use, low external component count and fast transient response. The device can also be used for other point-of-load (POL) regulation applications requiring up to 6 A. In addition, the device supports full, 6-A, output sinking current capability with tight voltage regulation.

The device features two switching frequency settings (600 kHz and 1 MHz), integrated droop support, external tracking capability, pre-bias startup, output soft discharge, integrated bootstrap switch, power good function, V5IN pin UVLO protection, and supports both ceramic and SP/POSCAP capacitors. It supports input voltages up to 6.0 V, and output voltages adjustable from 0.45 V to 2.0 V.

The TPS53317A device is available in the 3.5 mm × 4 mm, 20-pin, VQFN package (Green RoHs compliant and Pb free) with TI proprietary Integrated MOSFET and packaging technology and is specified from –40°C to 85°C.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS53317A	VQFN (20)	3.50 mm × 4.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Application

4 Revision History

Changes from * Revision (November 2015) to A Revision

Updated document status from Product Preview to Production Data. Go

5 Pin Configuration and Functions

RGB Package

20-Pin VQFN

Top View

Pin Functions

PIN		I/O⁽¹⁾	DESCRIPTION
NAME	NO.	I/O⁽¹⁾	DESCRIPTION
BST	16	I	Power supply for internal high-side gate driver. Connect a 0.1-µF bootstrap capacitor between this pin and the SW pin. Include a series boot resistor when the voltage spike on switching node is above 7 V.
COMP	8	O	Connect an R-C-C network between this pin and VREF for loop compensation.
EN	17	I	Enable pin (3.3-V logic compatible).
GND	6	–	Analog ground.
MODE	18	I	Allows selection of different operation modes. (See Table 1)
PGND	1	G	Power ground.
	2
	3
PGOOD	19	O	Open drain power good output. Connect pullup resistor.
REFIN	9	I	External tracking reference input. Apply voltage between 0.45 V to 2.0 V. For non-tracking mode, connect REFIN to VREF via resistor divider.
SW	11	I/O	Switching node output.
	12
	13
	14
	15
V5IN	20	I	5-V power supply for analog circuits and gate drive.
VIN	4	I	Power supply input pin.
VIN	5	I	Power supply input pin.
VOUT	10	I	Output voltage monitor input pin.
VREF	7	O	2.0-V reference output. Connect a ceramic capacitor with a value of 0.22-µF or greater between this pin and GND.

(1) I = Input, O = Output, G = Ground

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Input voltage range	BST (with respect to SW), V5IN, VIN	–0.3	7	V
	BST	–0.3	14
	EN	–0.3	7
	MODE, REFIN	–0.3	3.6
	VOUT	–1	3.6
Output voltage range	SW	–2	7	V
	SW (transient 20 ns and E = 5 µJ)	–3
	COMP, VREF	–0.3	3.6
	PGOOD	–0.3	7
	PGND	–0.3	0.3
Operating junction temperature, T_J		–40	150	˚C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds			300	˚C
Storage temperature, T_stg		–55	150	˚C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
Input voltage range	BST (with respect to SW), EN, VIN	–0.1		6.5	V
	V5IN	4.5		6.5
	BST	–0.1		13.5
	SW	–1.0		6.5
	VOUT, MODE, REFIN	–0.1		3.5
Output voltage range	COMP	–0.1		3.5	V
	VREF		2
	PGOOD	–0.1		6.5
	PGND	–0.1		0.1
Operating temperature range, T_A		-40		85	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS53317A	UNIT
		RGB (VQFN)
		20 PINS
R_θJA	Junction-to-ambient thermal resistance	35.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	39.6	°C/W
R_θJB	Junction-to-board thermal resistance	12.4	°C/W
ψ_JT	Junction-to-top characterization parameter	0.5	°C/W
ψ_JB	Junction-to-board characterization parameter	12.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended free-air temperature range, V_V5IN = 5.0 V, PGND = GND (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY: VOLTAGE, CURRENTS AND 5-V UVLO
I_VINSD	VIN shutdown current	EN = 'LO'		0.02	5	µA
V_V5IN	V5IN supply voltage	V5IN voltage range	4.5	5.0	6.5	V
I_V5IN	V5IN supply current	EN =’HI’, V5IN supply current, f_SW = 600 kHz		1.1	2	mA
I_V5INSD	V5IN shutdown current	EN = ‘LO’, V5IN shutdown current		0.2	7.0	µA
V_V5UVLO	V5IN UVLO	Ramp up; EN = 'HI'	4.20	4.37	4.50	V
V_V5UVHYS	V5IN UVLO hysteresis	Falling hysteresis		440		mV
V_VREFUVLO	REF UVLO⁽¹⁾	Rising edge of VREF, EN = 'HI'		1.8		V
V_VREFUVHYS	REF UVLO hysteresis⁽¹⁾			100		mV
V_POR5VFILT	Reset	OVP latch is reset by V5IN falling below the reset threshold	1.5	2.3	3.1	V
VOLTAGE FEEDBACK LOOP: VREF, VOUT, AND VOLTAGE GM AMPLIFIER
V_OUTTOL	Output voltage accuracy	V_REFIN = 1 V, No droop	–1%	0%	1%
V_OUTTOL	Output voltage accuracy	V_REFIN = 0.6 V, No droop	–1%	0%	1%
V_VREF	VREF	I_VREF= 0 µA	1.98	2.00	2.02	V
V_VREF	VREF	I_VREF= 50 µA	1.975	2.000	2.025	V
I_REFSNK	VREF sink current	V_VREF = 2.05 V		2.5		mA
g_M	Transconductance			1.00		mS
V_CM	Common mode input voltage range⁽¹⁾		0		2	V
V_DM	Differential mode input voltage		0		80	mV
I_COMPSNK	COMP pin maximum sinking current	V_COMP = 2 V, (V_REFIN – V_OUT) = 80 mV		80		µA
I_COMPSRC	COMP pin maximum sourcing current	V_COMP = 2 V		-80		µA
V_OFFSET	Input offset voltage	T_A = 25°C		0		mV
R_DSCH	Output voltage discharge resistance			42		Ω
f_–3dbVL	–3dB Frequency⁽¹⁾		4.5	6.0	7.5	MHz
CURRENT SENSE: CURRENT SENSE AMPLIFIER, OVERCURRENT AND ZERO CROSSING
A_CSINT	Internal current sense gain	Gain from the current of the low-side FET to PWM comparator when PWM = "OFF"	43	53	57	mV/A
I_OCL	Positive overcurrent limit (valley)			7.6		A
I_OCL(neg)	Negative overcurrent limit (valley)			–9.3		A
V_ZXOFF	Zero crossing comp internal offset			0		mV
PROTECTION: OVP, UVP, PGOOD, and THERMAL SHUTDOWN
V_PGDLL	PGOOD deassert to lower (PGOOD → Low)	Measured at the VOUT pin wrt/ V_REFIN		84%
V_PGHYSHL	PGOOD high hysteresis			8%
V_PGDLH	PGOOD de-assert to higher (PGOOD → Low)	Measured at the VOUT pin wrt/ V_REFIN		116%
V_PGHYSHH	PGOOD high hysteresis			-8%
V_INMINPG	Minimum VIN voltage for valid PGOOD	Measured at the VIN pin with a 2-mA sink current on PGOOD pin. V5IN is grounded here.⁽³⁾	0.9	1.3	1.5	V
V_OVP	OVP threshold	Measured at the VOUT pin wrt/ V_REFIN,V_REFIN= 1 V	117%	120%	123%
V_UVP	UVP threshold	Measured at the VOUT pin wrt/ V_REFIN, device latches OFF, begins soft-stop,V_REFIN= 1 V	65%	68%	71%
TH_SD	Thermal shutdown⁽¹⁾	Latch off controller, attempt soft-stop.		145		°C
TH_SD_(hys)	Thermal Shutdown hysteresis⁽¹⁾	Controller re-starts after temperature has dropped		10		°C
DRIVERS: BOOT STRAP SWITCH
R_DSONBST	Internal BST switch on-resistance	I_BST = 10 mA, T_A = 25°C			10	Ω
I_BSTLK	Internal BST switch leakage current	V_BST = 14 V, V_SW = 7 V			1	µA
TIMERS: ON-TIME, MINIMUM OFF-TIME, SS, AND I/O TIMINGS
t_ONESHOTC	PWM one-shot⁽¹⁾	V_VIN = 5 V, V_VOUT = 1.05 V, f_SW = 1 MHz		210		ns
t_ONESHOTC	PWM one-shot⁽¹⁾	V_VIN = 5 V, V_VOUT = 1.05 V, f_SW = 600 kHz		310		ns
t_MIN(off)	Minimum OFF time	V_VIN = 5 V, V_VOUT = 1.05 V, f_SW = 1 MHz, DRVL on, SW = PGND, V_VOUT < V_REFIN		270		ns
t_INT(SS)	Soft-start time	From V_OUT ramp starting to V_OUT =95%, default setting		1.6		ms
t_INT(SSDLY)	Internal soft-start delay time	From V_VREF = 2 V to V_OUT is ready to ramp up		260		µs
t_PGDDLY	PGOOD startup delay time	At external tracking, the time from VOUT is ready to ramp up		8		ms
t_PGDPDLYH	PGOOD high propagation delay time	50 mV over drive, rising edge	0.8	1	1.2	ms
t_PGDPDLYL	PGOOD low propagation delay time	50 mV over drive, falling edge		10		µs
t_OVPDLY	OVP delay time	Time from the VOUT pin out of +20% of REFIN to OVP fault		10		µs
t_UVDLYEN	Undervoltage fault enable delay	Time from EN_INT going high to undervoltage fault is ready		2		ms
t_UVDLYEN	Undervoltage fault enable delay	External tracking from VOUT ramp starts		8		ms
t_UVPDLY	UVP delay time	Time from the VOUT pin out of –32% of REFIN to UVP fault		256		µs
LOGIC PINS: I/O VOLTAGE AND CURRENT
	PGOOD pull-down voltage	PGOOD low impedance, I_SINK = 4 mA, V_V5IN= 4.5 V			0.3	V
	PGOOD leakage current	PGOOD high impedance, forced to 5.5 V	–1	0	1	µA
	EN logic high	EN, VCCP logic	2			V
	EN logic low	EN, VCCP logic			0.5	V
	EN input current				1	µA
	MODE threshold voltage⁽²⁾	Threshold 1	80	130	180	mV
		Threshold 2	200	250	300
		Threshold 3	370	420	470
		Threshold 4	550	600	650
		Threshold 5	830	880	930
		Threshold 6	1200	1250	1300
		Threshold 7	1765	1800	1850
	MODE current			15		µA

(1) Ensured by design, not production tested.

(2) See Table 1 for descriptions of MODE parameters.

(3) If V5IN is higher than 1.5 V, PGOOD is valid regardless of the voltage applied at VIN. This is based on bench testing.

6.6 Typical Characteristics

Characterization data tested using the TPS53317AEVM-726 where the external tracking input sets the output voltage and operates in non-droop mode. See SLUUBD2 for detailed configuration.