TPS53317A 6-A Output, D-CAP+ Mode, Synchronous Step-Down, Integrated-FET Converter for DDR Memory Termination
1 Features
- TI-Proprietary Integrated MOSFET and Packaging Technology
- Supports DDR Memory Termination with up to 6-A Continuous Output Source or Sink Current
- External Tracking
- Minimum External Components Count
- 0.9-V to 6-V Conversion Voltage
- D-CAP+™ Mode Architecture
- Supports All MLCC Output Capacitors and SP/POSCAP
- Selectable SKIP Mode or Forced CCM
- Optimized Efficiency at Light and Heavy Loads
- Selectable 600-kHz or 1-MHz Switching Frequency
- Selectable Overcurrent Limit (OCL)
- Overvoltage, Over-Temperature and Hiccup Undervoltage Protection
- Adjustable Output Voltage from 0.45 V to 2 V
- 3.5 mm × 4 mm, 20-Pin, VQFN Package
2 Applications
- Memory Termination Regulator for DDR, DDR2, DDR3, DDR3L, and DDR4
- VTT Termination
- Low-Voltage Applications for 0.9-V to 6-V Input Rails
3 Description
The TPS53317A device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ VDDQ with both sink and source capability. The TPS53317A device employs D-CAP+ mode operation that provides ease of use, low external component count and fast transient response. The device can also be used for other point-of-load (POL) regulation applications requiring up to 6 A. In addition, the device supports full, 6-A, output sinking current capability with tight voltage regulation.
The device features two switching frequency settings (600 kHz and 1 MHz), integrated droop support, external tracking capability, pre-bias startup, output soft discharge, integrated bootstrap switch, power good function, V5IN pin UVLO protection, and supports both ceramic and SP/POSCAP capacitors. It supports input voltages up to 6.0 V, and output voltages adjustable from 0.45 V to 2.0 V.
The TPS53317A device is available in the 3.5 mm × 4 mm, 20-pin, VQFN package (Green RoHs compliant and Pb free) with TI proprietary Integrated MOSFET and packaging technology and is specified from –40°C to 85°C.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| TPS53317A | VQFN (20) | 3.50 mm × 4.00 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
Simplified Application
4 Revision History
Changes from * Revision (November 2015) to A Revision
- Updated document status from Product Preview to Production Data. Go
5 Pin Configuration and Functions
Pin Functions
| PIN | I/O(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| BST | 16 | I | Power supply for internal high-side gate driver. Connect a 0.1-µF bootstrap capacitor between this pin and the SW pin. Include a series boot resistor when the voltage spike on switching node is above 7 V. |
| COMP | 8 | O | Connect an R-C-C network between this pin and VREF for loop compensation. |
| EN | 17 | I | Enable pin (3.3-V logic compatible). |
| GND | 6 | – | Analog ground. |
| MODE | 18 | I | Allows selection of different operation modes. (See Table 1) |
| PGND | 1 | G | Power ground. |
| 2 | |||
| 3 | |||
| PGOOD | 19 | O | Open drain power good output. Connect pullup resistor. |
| REFIN | 9 | I | External tracking reference input. Apply voltage between 0.45 V to 2.0 V. For non-tracking mode, connect REFIN to VREF via resistor divider. |
| SW | 11 | I/O | Switching node output. |
| 12 | |||
| 13 | |||
| 14 | |||
| 15 | |||
| V5IN | 20 | I | 5-V power supply for analog circuits and gate drive. |
| VIN | 4 | I | Power supply input pin. |
| 5 | |||
| VOUT | 10 | I | Output voltage monitor input pin. |
| VREF | 7 | O | 2.0-V reference output. Connect a ceramic capacitor with a value of 0.22-µF or greater between this pin and GND. |
