TPS53632G D-CAP+™ Half-Bridge PWM Controller Optimized for GaN-based 48-V DC/DC Converter with I2C Interface

1 Features

Valley Current Mode with Constant ON Time Control
Lossless Current Sensing Scheme
I²C Interface for VID Control and Telemetry
Programmable I²C Addresses up to Eight Devices
Switching Frequency up to 1 MHz
Digital Current Monitor
7-Bit, DAC Output Range: 0.50-V to 1.52-V with 10-mV Step
Accurate, Adjustable Voltage Positioning or Zero Slope Load-Line
Selectable, 8-Level Current Limit
Adjustable Output Slew Rate Control
Default Boot Voltage: 1.00 V
Small, 4-mm × 4-mm, 32-Pin, VQFN, PowerPAD Package

2 Applications

48-V Point-of-Load (POL) for Data Center and Telecommunication
Wide Input Range Power Supplies for Industrial

3 Description

The TPS53632G device is a half-bridge PWM controller with D-CAP+™ architecture that provides fast transient response, lowest output capacitance and high efficiency in single stage conversion directly from 48-V bus. The TPS53632G device supports the standard I²C Rev 3.0 interface for dynamic control of the output voltage and current monitor telemetry. Paired with TI GaN power stages and drivers, the TPS53632G can switch up to 1 MHz to minimize magnetic component size and reduce overall board space. The LMG5200 GaN power stage is designed specifically for this controller to achieve high frequency and efficiency as high as 92% with 48-V to 1-V conversion.

Other features include adjustable control of output slew rate and voltage positioning. In addition, the TPS53632G device can be used along with other TI discrete power MOSFETs and drivers for silicon-based half bridge solutions. The TPS53632G device is packaged in a space saving, thermally enhanced, 32-pin VQFN package and is rated to operate at a range between –10°C and 105°C.

Device Information

PART NUMBER	PACKAGE	BODY SIZE
TPS53632G	VQFN	4 mm × 4 mm

WHITESPACE

Simplified Schematic

4 Revision History

Changes from * Revision (April 2016) to A Revision

Updated document status from Product Preview to Production DataGo

5 Pin Configuration and Functions

RSM Package

32-Pin QFN

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
COMP	26	I	Error amplifier summing node. Resistors between the VREF pin and the COMP pin (R_COMP) and between the COMP pin and the DROOP pin (R_DROOP) set the droop gain.
CSP1	17	I	Positive current sense inputs. Connect to the most positive node of current sense resistor or inductor DCR sense network. Tie CSP2 or CSP1 (in that order) to a 3.3-V supply to disable the phase.
CSP2	20
PU3	21		Connect to 3.3-V supply.
CSN1	18	I	Negative current sense inputs. Connect to the most negative node of current sense resistor or inductor DCR sense network. CSN1 has a secondary OVP comparator and includes the soft-stop, pull-down transistor.
CSN2	19	I
NC	22	–	No connect.
DROOP	25	O	Error amplifier output. A resistor pair between this pin and the VREF pin and between the COMP pin and this pin sets the droop gain. A_DROOP = 1 + R_DROOP / R_COMP.
EN	8	I	Enable. 100-ns de-bounce. Regulator enters low-power mode, but retains start-up settings when brought low.
FREQ-P	10	I	A resistor between this pin and GND sets the per-phase switching frequency. Add a resistor to VREF to disable dynamic phase add and drop operation.
GFB	23	I	Voltage sense return. Tie to GND on PCB with a 10-Ω resistor to provide feedback when the microprocessor is not populated.
GND	29	–	Analog circuit reference. Tie this pin to a quiet point on the ground plane.
IMON	13	O	Analog current monitor output. V_IMON = ΣV_ISENSE × (1 + R_IMON/R_OCP).
OCP-I	12	I/O	Voltage divider to IMON. Resistor ratio sets the IMON gain (see IMON pin). A resistor between this pin and GND (R_OCP) selects 1 of 8 OCP levels (per phase, latched at start-up).
PU	9	I	Pull-up to VREF through 10-kΩ resistor.
PGOOD	3	O	Power good output. Open-drain.
PWM-HI	6	O	PWM controls for the external driver; 5-V logic level. Controller forces signal to the tri-state level when needed.
PWM-LO	5	O
NC	4	–	No connect.
NC	30	–	No connect.
NC	32	–	No connect.
RAMP	11	I	Voltage divider to VREF. A resistor to GND sets the ramp setting voltage. The RAMP setting can be used to override the factory ramp setting.
SCL	31	I	Serial digital clock line.
SDA	1	I/O	Serial digital I/O line.
SKIP	7	O	When high, the driver enters FCCM mode; otherwise, the driver is in DCM mode. Driving the tri-state level on this pin puts the drivers into a low power sleep mode.
SLEWA	15	I	The voltage sets the 3 LSBs of the I²C address. The resistance to GND selects 1 of 8 slew rates. The start-up slew rate (EN transitions high) is SLEWRATE/2. The ADDRESS and SLEWRATE values are latched at start-up.
VINTF	14	I	Input voltage to interface logic. Voltage level can be between 1.62 V and 3.5 V.
V5A	28	I	5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with ceramic capacitor with a value of at least 1 µF.
VBUS	16	I	The VBUS pin provides input voltage information to the on-time circuits for both converters.
VDD	2	I	3.3-V digital power input. Bypass this pin to GND with a capacitor with a value of at least 1 µF.
VFB	24	I	Voltage sense line. Tie directly to V_OUT sense point of processor. Tie to V_OUT on PCB with a 10-Ω resistor to provide feedback when the microprocessor is not populated. The resistance between VFB and GFB is > 1 MΩ
VREF	27	O	1.7-V, 500-µA reference. Bypass to GND with a 0.22-µF ceramic capacitor.
PAD	GND	–	Thermal pad Tie to the ground plane with multiple vias.