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  • TPS53647 4-Phase, D-CAP+, Step-Down, Buck Controller with NVM and PMBus™ Interface for ASIC Power and High-Current Point-of-Load

    • SLUSC39B June   2015  – February 2017 TPS53647

      PRODUCTION DATA.  

  • CONTENTS
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  • TPS53647 4-Phase, D-CAP+, Step-Down, Buck Controller with NVM and PMBus™ Interface for ASIC Power and High-Current Point-of-Load
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I/O Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  V3R3 LDO
      2. 7.3.2  PWM Operation
      3. 7.3.3  Current Sense and IMON Calculation
      4. 7.3.4  Setting the Load-Line (DROOP)
      5. 7.3.5  Load Transitions
      6. 7.3.6  Overshoot Reduction (OSR)
      7. 7.3.7  Undershoot Reduction (USR)
      8. 7.3.8  AutoBalance™ Current Sharing
      9. 7.3.9  Phase Overlap
      10. 7.3.10 VID
      11. 7.3.11 PWM and SKIP Signals
      12. 7.3.12 TSEN (Thermal Sense) Pin
      13. 7.3.13 RESET Function
      14. 7.3.14 Input UVLO
      15. 7.3.15 V5 Pin Undervoltage Lockout (UVLO)
      16. 7.3.16 Output Undervoltage Protection (UVP)
      17. 7.3.17 Overvoltage Protection (OVP)
      18. 7.3.18 Overcurrent Limit (OCL) and Overcurrent Protection (OCP)
      19. 7.3.19 Over Temperature Protection (OTP)
      20. 7.3.20 VR_HOT and VR_FAULT Indication
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 User Selections
        1. 7.5.1.1  Switching Frequency
        2. 7.5.1.2  IMAX Information
        3. 7.5.1.3  Boot Voltage
        4. 7.5.1.4  Per-Phase Overcurrent Limit (OCL) Level
        5. 7.5.1.5  Overshoot Reduction (OSR) and Undershoot Reduction (USR) Levels
        6. 7.5.1.6  Slew Rate Selection
        7. 7.5.1.7  Mode Selections
        8. 7.5.1.8  Soft Start Slew Rate and PMBus Addresses
        9. 7.5.1.9  Ramp Selection
        10. 7.5.1.10 Maximum Active Phase Numbers
        11. 7.5.1.11 Pinstrap Mode Settings
        12. 7.5.1.12 NVM Default Settings
        13. 7.5.1.13 4-Phase Application
      2. 7.5.2 Supported Protections and Fault Reports
      3. 7.5.3 Supported PMBus Address and Commands Summary
        1. 7.5.3.1 Address Selection
        2. 7.5.3.2 Commands Summary
    6. 7.6 Register Maps
      1. 7.6.1 PMBus Description
        1. 7.6.1.1 PMBus General
        2. 7.6.1.2 PMBus Connections
        3. 7.6.1.3 Supported Data Formats
        4. 7.6.1.4 PMBus Command Format
      2. 7.6.2 PMBus Functionality
        1. 7.6.2.1 PMBus Address
        2. 7.6.2.2 Pin Strap Settings
        3. 7.6.2.3 Supported PMBus Commands
          1. 7.6.2.3.1  OPERATION (01h)
          2. 7.6.2.3.2  ON_OFF_CONFIG (02h)
          3. 7.6.2.3.3  CLEAR_FAULTS (03h)
          4. 7.6.2.3.4  WRITE_PROTECT (10h)
          5. 7.6.2.3.5  STORE_DEFAULT_ALL (11h)
          6. 7.6.2.3.6  RESTORE_DEFAULT_ALL (12h)
          7. 7.6.2.3.7  CAPABILITY (19h)
          8. 7.6.2.3.8  VOUT_MODE (20h)
          9. 7.6.2.3.9  VOUT_COMMAND (21h)
          10. 7.6.2.3.10 VOUT_MAX (24h)
          11. 7.6.2.3.11 VOUT_MARGIN_HIGH (25h)
          12. 7.6.2.3.12 VOUT_MARGIN_LOW (26h)
          13. 7.6.2.3.13 IOUT_CAL_OFFSET (39h)
          14. 7.6.2.3.14 VOUT_OV_FAULT_RESPONSE (41h)
          15. 7.6.2.3.15 VOUT_UV_FAULT_RESPONSE (45h)
          16. 7.6.2.3.16 IOUT_OC_FAULT_LIMIT (46h)
          17. 7.6.2.3.17 IOUT_OC_FAULT_RESPONSE (47h)
          18. 7.6.2.3.18 IOUT_OC_WARN_LIMIT (4Ah)
          19. 7.6.2.3.19 OT_FAULT_LIMIT (4Fh)
          20. 7.6.2.3.20 OT_FAULT_RESPONSE (50h)
          21. 7.6.2.3.21 OT_WARN_LIMIT (51h)
          22. 7.6.2.3.22 VIN_OV_FAULT_LIMIT (55h)
          23. 7.6.2.3.23 IIN_OC_FAULT_LIMIT (5Bh)
          24. 7.6.2.3.24 IIN_OC_FAULT_RESPONSE (5Ch)
          25. 7.6.2.3.25 IIN_OC_WARN_LIMIT (5Dh)
          26. 7.6.2.3.26 STATUS_BYTE (78h)
          27. 7.6.2.3.27 STATUS_WORD (79h)
          28. 7.6.2.3.28 STATUS_VOUT (7Ah)
          29. 7.6.2.3.29 STATUS_IOUT (7Bh)
          30. 7.6.2.3.30 STATUS_INPUT (7Ch)
          31. 7.6.2.3.31 STATUS_TEMPERATURE (7Dh)
          32. 7.6.2.3.32 STATUS_CML (7Eh)
          33. 7.6.2.3.33 STATUS_MFR_SPECIFIC (80h)
          34. 7.6.2.3.34 READ_VIN (88h)
          35. 7.6.2.3.35 READ_IIN (89h)
          36. 7.6.2.3.36 READ_VOUT (8Bh)
          37. 7.6.2.3.37 READ_IOUT (8Ch)
          38. 7.6.2.3.38 READ_TEMPERATURE_1 (8Dh)
          39. 7.6.2.3.39 READ_POUT (96h)
          40. 7.6.2.3.40 READ_PIN (97h)
          41. 7.6.2.3.41 PMBus_REVISION (98h)
          42. 7.6.2.3.42 MFR_ID (99h)
          43. 7.6.2.3.43 MFR_MODEL (9Ah)
          44. 7.6.2.3.44 MFR_REVISION (9Bh)
          45. 7.6.2.3.45 MFR_DATE (9Dh)
          46. 7.6.2.3.46 MFR_VOUT_MIN (A4h)
          47. 7.6.2.3.47 MFR_SPECIFIC_00 (Per-Phase Overcurrent Limit) (D0h)
          48. 7.6.2.3.48 MFR_SPECIFIC_01 (Telemetry Averaging Time) (D1h)
          49. 7.6.2.3.49 MFR_SPECIFIC_04 (Read VOUT) (D4h)
          50. 7.6.2.3.50 MFR_SPECIFIC_05 (VOUT Trim) (D5h)
          51. 7.6.2.3.51 MFR_SPECIFIC_07 (Additional Function Bits) (D7h)
          52. 7.6.2.3.52 MFR_SPECIFIC_08 (Droop) (D8h)
          53. 7.6.2.3.53 MFR_SPECIFIC_09 (OSR/USR) (D9h)
          54. 7.6.2.3.54 MFR_SPECIFIC_10 (Maximum Operating Current) (DAh)
          55. 7.6.2.3.55 MFR_SPECIFIC_11 (VBOOT) (DBh)
          56. 7.6.2.3.56 MFR_SPECIFIC_12 (Switching Frequency and TRISE) (DCh)
          57. 7.6.2.3.57 MFR_SPECIFIC_13 (Slew Rate and Other Operation Modes) (DDh)
          58. 7.6.2.3.58 MFR_SPECIFIC_14 (Ramp Height) (DEh)
          59. 7.6.2.3.59 MFR_SPECIFIC_15 (Dynamic Phase Shedding Thresholds) (DFh)
          60. 7.6.2.3.60 MFR_SPECIFIC_16 (VIN UVLO) (E0h)
          61. 7.6.2.3.61 MFR_SPECIFIC_20 (Maximum Operational Phase Number) (E4h)
          62. 7.6.2.3.62 MFR_SPECIFIC_22 ( VOUT_UV_FAULT_threshold) (E6h)
          63. 7.6.2.3.63 MFR_SPECIFIC_44 (DEVICE_CODE) (FCh)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Select the Switching Frequency
        2. 8.2.2.2  Set the Maximum Output Current (IMAX)
        3. 8.2.2.3  Select the Soft-Start Slew Rate
        4. 8.2.2.4  Select the Operation Mode
        5. 8.2.2.5  Choose Inductor
        6. 8.2.2.6  Select the Per-Phase Valley Current Limit And Ramp Level
        7. 8.2.2.7  Set the Load-Line
        8. 8.2.2.8  Set the BOOT Voltage
        9. 8.2.2.9  Set OSR/USR Thresholds to Improve Load Transient Performance
        10. 8.2.2.10 Digital Current Monitor (IMON) Gain and Filter Setting
        11. 8.2.2.11 Compensation Design
        12. 8.2.2.12 Set PMBus Addresses
        13. 8.2.2.13 Programming the Device with the PMBus
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Schematic Review Checklist
      2. 10.1.2 PCB Design Guidelines
        1. 10.1.2.1 Layer Stack-up, 8-Layer PCB as example
        2. 10.1.2.2 Current Sensing Lines
        3. 10.1.2.3 Feedback Voltage Sensing Lines
        4. 10.1.2.4 PWM Lines
        5. 10.1.2.5 Power Chain Symmetry
        6. 10.1.2.6 Placing Analog Signal Components
        7. 10.1.2.7 Grounding Recommendations
        8. 10.1.2.8 TI Smart Power Stage CSD95372BQ5MC
          1. 10.1.2.8.1 Electrical Performance
          2. 10.1.2.8.2 Thermal Performance
          3. 10.1.2.8.3 Sensing Performance
        9. 10.1.2.9 Power Delivery and Power Density
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RTA|40
    • MPQF134A
Thermal pad, mechanical data (Package|Pins)
  • RTA|40
    • QFND055H
Orderable Information
  • slusc39b_oa
  • slusc39b_pm
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

TPS53647 4-Phase, D-CAP+, Step-Down, Buck Controller with NVM and PMBus™ Interface for ASIC Power and High-Current Point-of-Load

1 Features

  • 8-bit Selectable BOOT Voltage via Pinstrap or NVM: 0.5 V to 2.5 V (down to 5-mV Step)
  • 1-, 2-, 3-, or 4- Phase Operation
  • PMBus™ System Interface for Telemetry of Voltage, Current, Power, Temperature, and Fault Conditions
  • 1.8-V and 3.3-V PMBus Bias Compatible
  • Fault Reporting: Output Voltage, Output Current, and Temperature
  • Configurable with Non-Volatile Memory (NVM) or Resistor Pinstrap
  • 16 Levels of Programmable OCP with Pinstrap or NVM
  • Fast Transient with DCAP+™Control
  • Optimized Efficiency at Light and Heavy Loads
  • Support Pre-Bias Startup
  • Phase Current Imbalance Detection and Reporting
  • 8 Independent Levels of Overshoot Reduction (OSR) and Undershoot Reduction (USR)
  • Driverless Configuration for Efficient High-Frequency Switching
  • Fully Compatible with CSD95372BQ5MC NexFET™ Power Stage
  • Accurate, Adjustable Voltage Positioning
  • 300-kHz to 1-MHz Frequency Selections with Closed-loop Frequency Control
  • Patented AutoBalance™ Phase Balancing
  • Uses TI’s Fusion Digital Power Designer GUI
  • Dynamic Phase Shedding with Programmable Current Threshold
  • Conversion Voltage Range: 4.5 V to 17 V
  • Small, 6 mm × 6 mm, 40-Pin, QFN, PowerPAD™ Package

2 Applications

  • Application-Specific Integrated Circuit (ASIC) Power in Communications Equipment
  • High Density Power Solutions
  • Server Power
  • Smart Power Systems

3 Description

The TPS53647 is a high-current, multi-phase, step-down controller. The device offers built-in non volatile memory (NVM) and PMBus interface. It is compatible with the NexFET power stages (CSD95372BQ5MC). The TPS53647 provides 8-bit BOOT voltage selection covering output voltage from 0.5 V to 2.5 V, with steps as small as 5 mV, which is ideal for high current application with accurate output voltage setting. Advanced control features such as D-CAP+ architecture with undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, lowest output capacitance, and high efficiency. The TPS53647 also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at light loads. In addition, the TPS53647 supports the PMBus communication interface with systems for telemetry of voltage, current, power, temperature, and fault conditions. Some of the configurations can be programmed by pinstrap or PMBus and stored in non-volatile memory to minimize the external component count.

The TPS53647 is offered in a space saving, thermally enhanced 40-pin QFN package and is rated to operate from –40°C to 125°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS53647 QFN (40) 6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

TPS53647 fp_simp_app_tps53647_slusc39.gif

4 Revision History

Changes from A Revision (September 2016) to B Revision

  • Updated V3R3 LDO sectionGo
  • Added temperature default value VR_HOT and VR_FAULT Indication sectionGo
  • Corrected factory default value of VOUT_OV_FAULT_RESPONSE command in Table 7Go
  • Corrected factory default value of VIN_OV_FAULT_LIMIT command in Table 7Go
  • Corrected factory default value of MFR_ID command in Table 7Go
  • Corrected factory default value of MFR_SPECIFIC_44 command in Table 7Go

Changes from * Revision (June 2015) to A Revision

  • Updated the VADDR-TRISE condition of the PADDR specification in the Electrical Characteristics table from "1.647 V" to "1.615 V" Go
  • Updated the VOCL-R condition of the IOCLx specification in the Electrical Characteristics table from "0.8 V" to "0.85 V" Go
  • Updated the VOCL-R condition of the IOCLx specification in the Electrical Characteristics table from "1.0 V" to "0.95 V" Go
  • Updated the VOCL-R condition of the VRAMP specification in the Electrical Characteristics table to "±50 mV" Go
  • Updated the VSLEW-MODE condition of the VMODE specification in the Electrical Characteristics table from " 1.647 V with ±20 mV tolerance" to "1.615 V with ±10 mV tolerance" Go
  • Updated the VO-USR condition of the VUSR specification in the Electrical Characteristics table from " VO-USR ≥ 1.55 V (USR OFF)" to "1.55 V ≤ VO-USR ≤ 1.6 V " Go
  • Updated the VVBOOT (B7B6B5B4) condition of the VBOOT specification in the Electrical Characteristics table from " 1.647 V with ±20 mV tolerance" to "1.615 V with ±10 mV tolerance" Go
  • Clarified the READ_VIN (88h) sectionGo
  • Corrected typographical error in READ_VOUT (8Bh) sectionGo
  • Clarified the READ_IOUT (8Ch) sectionGo
  • Clarified the READ_TEMPERATURE_1 (8Dh) sectionGo
  • Clarified the READ_POUT (96h) sectionGo
  • Clarified the READ_POUT (96h) sectionGo
  • Clarified the MFR_SPECIFIC_04 (Read VOUT) (D4h) sectionGo
  • Updated the MFR_SPECIFIC_14 (Ramp Height) (DEh) sectionGo
  • Clarified the Set the Load-Line sectionGo
  • Updated Table 79Go
  • Updated Table 82 Go
  • Added Receiving Notification of Documentation Updates sectionGo
  • Added Community Resources sectionGo

5 Pin Configuration and Functions

RTA Package
40-Pin QFN
Top View
TPS53647 pinout_rsb40_slusc39.gif
NC = No internal connection

Pin Functions

PIN I/O(1) DESCRIPTION
NAME NO.
ADDR-TRISE 28 I Voltage divider to VREF pin. A resistor (RADDR-TRISE) connected between this pin and GND sets the 3-bits. Bit 2 and bit 1 set the rise slew rate. Bit 0 Selects the LSB of BOOT voltage. The voltage (VADDR-TRISE) sets 4 bits PMBus address. The device latches these settings when V3R3 powers up.
COMP 11 O Output of the gM error amplifier. Resistors and capacitors connected between this pin and the VREF pin set the compensation.
CSP1 3 I Positive current sense inputs. Connect to the IOUT pin of TI smart power stages (ex: CSD95372BQ5MC). Tie CSP4, CSP3, or CSP2 to the V3R3 pin according to Table 3 to disable the corresponding phase.
CSP2 4
CSP3 5
CSP4 6
ENABLE 23 I VR enable. 1-V I/O level; 100-ns debounce.
F-IMAX 32 I Voltage divider to VREF pin. A resistor (RF-IMAX) connected between this pin and GND sets the operating frequency of the controller. The voltage level (VF-IMAX) sets the maximum operating current of the converter. The IMAX value is an 8-bit A/D where VF-IMAX = VVREF × IMAX / 255. Both are latched at V3R3 power-up.
GND 17 G Ground pin.
GND 20 G Connect these pins to GND. Note this is not IC ground pin.
22
IMON 2 O Analog current monitor output. TPS53647 q_vimon_slusc00.gif
ISUM 12 O A resistor (RISUM) connected between this pin and VREF pin determines the droop.
TPS53647 q_visum_slusc39.gif
(where n is the number of phases)
NC 7 — No connection. Leave the pin open or pull up to V3R3 pin.
8
33 — No connection.
34
OCL-R 1 I A resistor (ROCL-R) connected between this pin and GND and the voltage level (VOCL-R) select 1 of 16 OCL levels (per phase current-limit). VOCL-R also sets one of four RAMP levels. The device latches these settings when V3R3 powers up.
O-USR 30 I Voltage divider to VREF pin. A resistor (RO-USR) connected between this pin and GND selects one of seven OSR thresholds or OFF. The voltage level (VO-USR) sets one of seven USR levels or OFF. The device latches these settings when V3R3 powers up.
PMB_ALERT 25 O I2C PMBus interrupt line. Open drain. 3.3-V and 1.8-V logic level.
PMB_CLK 24 I I2C PMBus clock. 3.3-V and 1.8-V logic level.
PMB_DIO 26 I/O I2C PMBus digital I/O line. 3.3-V and 1.8-V logic level.
PWM1 38 O PWM signals for each phase
PWM2 37
PWM3 36
PWM4 35
RESET 21 I Reset pin. If this pin is low for more than 1000 ns, the controller pulls the output voltage to the VBOOT level.
SKIP-NVM 39 O A resistor (R SKIP-NVM) connected between this pin and GND sets either pinstrap or NVM configuration mode. This pin can also connect to the FCCM pin of TI smart power stages (ex: CSD95372BQ5MC) for SKIP or FCCM operation.
SLEW-MODE 29 I Voltage divider to VREF pin. A resistor (RSLEW-MODE) connected between this pin and GND sets 8 slew rates. The voltage level (VSLEW-MODE) sets 4-bit operation modes. Bit 7 for DAC mode (1 for VR12.0; 0 for VR12.5). Bit 6 for the 4-phase interleaving mode (1 for 1/3 and 2/4 two phase interleaving; 0 for 4 phase interleaving individually). Bit 4 for enabling dynamic phase add or drop (1 for enable; 0 for disable). Bit 3 sets zero load-line (1 for zero load-line; 0 for non-zero load-line) The device latches these settings when V3R3 powers up.
TSEN 40 I Connect to the TAO/FAULT pin of TI smart power stages (ex: CSD95372BQ5MC) to sense the highest temperature of the power stages and to sense the fault signal from the power stages.
V3R3 14 O 3.3-V LDO output. Bypass this pin to GND with a ceramic capacitor with a value of 1-µF or larger.
V5 15 P 5-V power input. Bypass this pin to GND with a ceramic capacitor with a value of 1-µF or larger. This pin is used to power all internal analog circuits.
VBOOT 31 I Voltage divider to VREF pin. A resistor (RVBOOT) connected between this pin and GND sets 3 bits (B[3:1]). The voltage level (VVBOOT) sets 4 bits (B[7:4]). The total 7 bits set 7 of 8 bits of VID of boot voltage (B[7:1]). The device latches these settings when V3R3 powers up.
VIN 16 P Input voltage supply. This pin is also used for input voltage sensing for on-time control and input undervoltage lockout (UVLO).
VR_RDY 18 O Power good open-drain output for the controller. This pin is typically pulled up to V3R3 pin through a resistor with a value of 3-kΩ or larger.
VR_FAULT 27 O VR fault indicator (open-drain). The failures include shorts of the high-side FETs, over temperature, output overvoltage, and overcurrent conditions of the input. The fault signal should be used on the platform to remove the power source either by firing a shunting SCR to blow a fuse or by turning off the AC power supply. When the failure occurs, the VR_FAULT pin is LOW. This pin is typically pulled up to V3R3 pin through a resistor with a value of 3-kΩ or larger. Leave this pin floating if not used.
VR_HOT 19 O Thermal flag open drain output. Active low. This pin is typically pulled up to V3R3 pin through a resistor with a value of 3-kΩ or larger. Leave this pin floating if not used.
VREF 13 O 1.7-V, 500-µA, LDO reference voltage. Bypass this pin to GND with a ceramic capacitor with a value of 0.33 µF. Connect the VREF pin to the REFIN pin of TI smart power stages (ex: CSD95372BQ5MC) as the current-sense reference voltage.
VSN 10 I Negative input of the remote voltage sense amplifier. Connect this pin directly to the GND of the load.
VSP 9 I Positive input of the remote voltage sense amplifier. Connect this pin directly to the load.
Thermal Pad GND Thermal pad. Connect the thermal pad to the ground plane with multiple vias.
(1) I = Input, O = Output, P = Power, I/O = Bi-directional, GND = ground

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN MAX UNIT
Input Voltage VIN –0.3 19 V
V5 –0.3 6
ADDR-TRISE, CSP1, CSP2, CSP3, CSP4, ENABLE, F-IMAX, OCL-R, O-USR, PMB_CLK, PMB_DIO, RESET, SLEW-MODE, VBOOT, VSP –0.3 3.6
TSEN –0.3 6
GND, VSN –0.3 0.3
Output Voltage VREF –0.3 1.8 V
IMON, ISUM,PMB_ALERT, PWM1, PWM2, PWM3, PWM4, SKIP-NVM, V3R3, VR_RDY, VR_FAULT, VR_HOT –0.3 3.6
COMP –0.3 6
Operating Junction Temperature, TJ –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal GND unless otherwise noted.

6.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –55 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) -2.5 2.5 kV
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) -1.5 1.5
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VI Input voltage VIN 4.5 12 17 V
TSEN -0.1 5.5
V5 4.5 5 5.5
ADDR-TRISE, F-IMAX, OCL-R, O-USR, SLEW-MODE, VBOOT 0.1 VVREF
CSP1, CSP2, CSP3, CSP4, VSP –0.1 2.5
ENABLE, PMB_CLK, PMB_DIO –0.1 3.5
GND, VSN –0.1 0.1
VO Output voltage VREF –0.1 1.72 V
V3R3 -0.1 3.3 3.5
IMON, ISUM, PMB_ALERT, PWM1, PWM2, PWM3, PWM4, SKIP-NVM, VR_RDY, VR_FAULT, VR_HOT –0.1 3.5
COMP –0.1 5.5
TA Operating free air temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS53647 UNIT
RTA (QFN)
40 PINS
RθJA Junction-to-ambient thermal resistance 30.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 14.2
RθJB Junction-to-board thermal resistance 6.9
ψJT Junction-to-top characterization parameter 0.2
ψJB Junction-to-board characterization parameter 6.8
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended free-air temperature range, VVIN = 12 V, VV5 = 5 V, VVSN = GND, VVSP = VOUT (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY: CURRENTS, UVLO, AND POWER-ON RESET
IVIN VIN supply current, 4-phase active VVDAC < VVSP < VVDAC + 100 mV, ENABLE = HI 115 µA
IV5 V5 supply current PMBus Idle, ENABLE = HI 6.1 7 mA
IV5SBY V5 standby current ENABLE = LO 2 2.6 mA
VV3R3 V3R3 output voltage IV3R3 = 0 A 3.2 3.3 3.4 V
VV3R3(dropout) V3R3 load regulation IV3R3 = 5 mA 100 mV
VV5UVLOH V5 UVLO OK threshold Ramp up 4.1 4.25 4.5 V
VV5UVLOL V5 UVLO fault threshold Ramp down 3.95 4.05 4.25 V
VHYS(V5) V5 UVLO hysteresis Hysteresis 0.15 0.23 0.3 V
VVINUVLO VIN UVLO voltage MFR_SPEC_16[1:0] = 00 4.2 4.5 4.7 V
MFR_SPEC_16[1:0] = 01 6.9 7.25 7.45
MFR_SPEC_16[1:0] = 10 8.6 9.0 9.25
MFR_SPEC_16[1:0] = 11 9.8 10.3 10.7
VHYS(VIN) VIN UVLO hysteresis voltage Hysteresis voltage 1 V
REFERENCES: DAC AND VREF
VVIDSTP VID Step size VR12.5: Change VID0 HI to LO to HI 10 mV
VR12.0: Change VID0 HI to LO to HI 5 mV
VDAC1 Closed Loop VSP tolerance VR12.0: 0.61 V ≤ VVSP ≤ 0.995 V, IOUT = 0 A , 0 °C ≤ TA≤ 85 °C –6 6.5 mV
VDAC2 Closed Loop VSP tolerance VR12.0: 1 V ≤ VVSP ≤ 1.52 V, ICOUT = 0 A, 0 °C ≤ TA≤ 85 °C –0.6 0.6 %
VDAC3 Closed Loop VSP tolerance VR12.5: 1.50V ≤ VVSP ≤ 2.50 V, IOUT = 0 A, 0 °C ≤ TA≤ 85 °C –1 1 %
VDAC4 Closed Loop VSP tolerance VR12.0: 0.61 V ≤ VVSP ≤ 0.995 V, IOUT = 0 A, –40°C ≤ TA≤ 125 °C –8 8 mV
VDAC5 Closed Loop VSP tolerance VR12.0: 1.0 V ≤ VVSP ≤ 1.52 V, IOUT = 0 A, –40 °C ≤ TA≤ 125 °C -0.8 0.8 %
VDAC6 Closed Loop VSP tolerance VR12.5: 1.50 V ≤ VVSP ≤ 2.50V, IOUT = 0 A, –40°C ≤ TA≤ 125 °C -1.1 1.0 %
VVREF VREF output 4.5 ≤ VV5 ≤ 5.5 V, IVREF = 0 A 1.685 1.70 1.717 V
VVREFSRC VREF output source IVREF = 0 to 500 µA –4 -1 mV
VVREFSNK VREF output sink IVREF = –500 to 0 µA 1 4 mV
CURRENT SENSE: AMPLIFIER AND PHASE BALANCING
GCSINT Internal current sense gain Gain from (CSPx – VREF ) to PWM comparator 1.0 V/V
COMPENSATOR: VOLTAGE POSITIONING AND AMPLIFIER
gM(isum) ISUM amplifier transconductance VVSP = 1.7 V 500 µS
gM(comp) COMP amplifier transconductance VVSP = 1.7 V 1000 µS
VCCLAMPN COMP amplifier negative clamp voltage (VVREF – VCOMP) VRAMP + 20 mV
VCCLAMPP COMP amplifier positive clamp voltage (VCOMP – VVREF) 2.1 2.2 2.3 V
VOLTAGE SENSE: VSP AND VSN
IVSP VSP input bias current Not in fault, disable or UVLO,
VVSP = VVDAC = 2.3 V, VVSN = 0 V		 300 µA
IVSN VSN input bias current Not in fault, disable or UVLO,
VVSP = VVDAC = 2.3 V, VVSN = 0 V		 -30 -23 µA
RSFTSTP Transistor resistance Connect to VSP 10 kΩ
LOGIC ( RESET, VR_RDY, VR_FAULT, VR_HOT, AND ENABLE) INTERFACE PINS: I/O VOLTAGE AND CURRENT
RRPGDL Open drain pull-down resistance VR_RDY, pulldown resistance at 0.31 V 36 50 Ω
IVRTTLK Open drain leakage current VR_HOT, VR_RDY, hi-Z leakage, apply 3.3 V in off state –2 0.2 2 µA
VRSTL RESET logic low RESET Pin 0.8 V
VRSTH RESET logic high RESET Pin 1.2 V
TRSTTDLY RESET Delay Time 1 µs
VENL ENABLE logic low 0.3 V
VENH ENABLE logic high 0.8 V
IENH I/O 1.1- V leakage Leakage current , VENABLE = 1.1 V 25 µA
PMBUS INTERFACE PINS: I/O VOLTAGE AND CURRENT
VPMBL PMBus pins logic low 0.8 V
VPMBH PMBus pins logic high 1.2 V
IPMBL Logic low input current VPMBus=0 V -10 10 µA
IPMBH Logic high input current VPMBus=1.8 V -10 10 µA
ADDR-TRISE PIN: PMBUS ADDRESS, SOFT START RISE TIME SETTING
SLRISE Soft start rise slew rate in terms of VOUT slew rate RADDR-TRISE ≤ 20 kΩ or RADDR-TRISE = 24 kΩ or MFR_SPEC_12<1:0> = 00b 1
RADDR-TRISE = 30 kΩ or RADDR-TRISE = 39 kΩ or MFR_SPEC_12<1:0> = 01b 1/2
RADDR-TRISE = 56 kΩ or RADDR-TRISE = 75 kΩ or MFR_SPEC_12<1:0> = 10b 1/4
RADDR-TRISE = 100 kΩ or RADDR-TRISE = 150 kΩ or MFR_SPEC_12<1:0> = 11b 1/8
BOOT BOOT voltage set (B0) RADDR-TRISE ≤ 20 kΩ or RADDR-TRISE = 30 kΩ or RADDR-TRISE = 56 kΩ or RADDR-TRISE = 100 kΩ, or MFR_SPEC_11 [0] = 0b 0
RADDR-TRISE = 24 kΩ or RADDR-TRISE = 39 kΩ or RADDR-TRISE = 75 kΩ or RADDR-TRISE = 150 kΩ, or MFR_SPEC_11 [0] = 1b 1
PADDR PMBus address bits set (11P40P2P1P0) VADDR-TRISE ≤ 0.053 V with ±20 mV tolerance 1100000
VADDR-TRISE = 0.159 V with ±20 mV tolerance 1100001
VADDR-TRISE = 0.266 V with ±20 mV tolerance 1100010
VADDR-TRISE = 0.372 V with ±20 mV tolerance 1100011
VADDR-TRISE = 0.478 V with ±20 mV tolerance 1100100
VADDR-TRISE = 0.584 V with ±20 mV tolerance 1100101
VADDR-TRISE = 0.691 V with ±20 mV tolerance 1100110
VADDR-TRISE = 0.797 V with ±20 mV tolerance 1100111
VADDR-TRISE = 0.903 V with ±20 mV tolerance 1110000
VADDR-TRISE = 1.009 V with ±20 mV tolerance 1110001
VADDR-TRISE = 1.116 V with ±20 mV tolerance 1110010
VADDR-TRISE = 1.222 V with ±20 mV tolerance 1110011
VADDR-TRISE = 1.328 V with ±20 mV tolerance 1110100
VADDR-TRISE = 1.434 V with ±20 mV tolerance 1110101
VADDR-TRISE = 1.541 V with ±20 mV tolerance 1110110
VADDR-TRISE = 1.615 V with ±10 mV tolerance 1110111
OCL-R PIN: OVERCURRENT THRESHOLDS AND RAMP SETTINGS
IOCLx Phase OCL level (CSPx-VREF)
(valley current-limit)		 ROCL-R = 20 kΩ and VOCL-R ≤ 0.85 V or
MFR_SPEC_00[3:0] = 0000b 		21 24 27 A
ROCL-R = 24 kΩ and VOCL-R ≤ 0.85 V or
MFR_SPEC_00[3:0] = 0001b 		25 27 30
ROCL-R = 30 kΩ and VOCL-R ≤ 0.85 V or
MFR_SPEC_00[3:0] = 0010b 		28 30 33
ROCL-R = 39 kΩ and VOCL-R ≤ 0.85 V or
MFR_SPEC_00[3:0] = 0011b 		31 33 36
ROCL-R = 56 kΩ and VOCL-R ≤ 0.85 V or
MFR_SPEC_00[3:0] = 0100b 		34 36 39
ROCL-R = 75 kΩ and VOCL-R ≤ 0.85 V or
MFR_SPEC_00[3:0] = 0101b 		37 39 42
ROCL-R = 100 kΩ and VOCL-R ≤ 0.85 V or
MFR_SPEC_00[3:0] = 0110b 		40 42 45
ROCL-R ≥ 150 kΩ and VOCL-R ≤ 0.85 V or
MFR_SPEC_00[3:0] = 0111b 		43 45 48
ROCL-R = 20 kΩ and VOCL-R ≥ 0.95 V or
MFR_SPEC_00[3:0] = 1000b 		46 48 51
ROCL-R = 24 kΩ and VOCL-R ≥ 0.95 V or
MFR_SPEC_00[3:0] = 1001b 		49 51 54
ROCL-R = 30 kΩ and VOCL-R ≥ 0.95 V or
MFR_SPEC_00[3:0] = 1010b 		52 54 57
ROCL-R = 39 kΩ and VOCL-R ≥ 0.95 V or
MFR_SPEC_00[3:0] = 1011b 		55 57 60
ROCL-R = 56 kΩ and VOCL-R ≥ 0.95 V or
MFR_SPEC_00[3:0] = 1100b 		58 60 63
ROCL-R = 75 kΩ and VOCL-R ≥ 0.95 V or
MFR_SPEC_00[3:0] = 1101b 		61 63 66
ROCL-R = 100 kΩ and VOCL-R ≥ 0.95 V or
MFR_SPEC_00[3:0] = 1110b 		64 66 69
ROCL-R ≥ 150 kΩ and VOCL-R ≥ 0.95 V or
MFR_SPEC_00[3:0] = 1111b 		67 69 72
VRAMP Ramp setting VOCL-R = 0.2 V ±50mV or VOCL-R = 1.0 V ±50mV or MFR_SPEC_14[2:0] = 001b 30 40 50 mVP_P
VOCL-R = 0.4 V ±50mV or VOCL-R = 1.2 V ±50mV or MFR_SPEC_14[2:0] = 011b 70 80 90
VOCL-R = 0.6 V ±50mV or VOCL-R = 1.4 V ±50mV or MFR_SPEC_14[2:0] = 110b 135 145 155
VOCL-R = 0.8 V ±50mV or VOCL-R = 1.6 V ±50mV or MFR_SPEC_14[2:0] = 111b 180 190 205
F-IMAX PIN: FREQUENCY AND IMAX SETTINGS
fSW Switching frequency (See Switching Characteristics)
IMAX IMAX values VF-IMAX(min) = 0.136V
IMAX=(VF-IMAX /VVREF × 256)-0.5		 18 20 22 A
VF-IMAX(min) = 0.403 V
IMAX=(VF-IMAX /VVREF × 256)-0.5		 58 60 62
VF-IMAX(min) = 0.536 V
IMAX=(VF-IMAX /VVREF × 256)-0.5		 78 80 82
VF-IMAX(min) = 0.803 V
IMAX=(VF-IMAX /VVREF × 256)-0.5		 118 120 122
SLEW-MODE PIN: SLEW RATES and MODE SELECTIONS
SLSET Slew rate setting RSLEW-MODE ≤ 20 kΩ
or MFR_SPEC_13[2:0] = 000b and MFR_SPEC_07[2] = 0b 		0.28 0.34 mV/µs
RSLEW-MODE = 24 kΩ
or MFR_SPEC_13[2:0] = 001b and MFR_SPEC_07[2] = 0b 		0.60 0.68
RSLEW-MODE = 30 kΩ
or MFR_SPEC_13[2:0] = 010b and MFR_SPEC_07[2] = 0b 		0.91 1.02
RSLEW-MODE = 39 kΩ
or MFR_SPEC_13[2:0] = 011b and MFR_SPEC_07[2] = 0b 		1.22 1.36
RSLEW-MODE = 56 kΩ
or MFR_SPEC_13[2:0] = 100b and MFR_SPEC_07[2] = 0b 		1.53 1.7
RSLEW-MODE = 75 kΩ
or MFR_SPEC_13[2:0] = 101b and MFR_SPEC_07[2] = 0b 		1.85 2.04
RSLEW-MODE = 100 kΩ
or MFR_SPEC_13[2:0] = 110b and MFR_SPEC_07[2] = 0b 		2.16 2.38
RSLEW-MODE ≥ 150 kΩ
or MFR_SPEC_13[2:0] = 111b and MFR_SPEC_07[2] = 0b 		2.48 2.74
RSLEW-MODE ≤ 20 kΩ
or MFR_SPEC_13[2:0] = 000b and MFR_SPEC_07[2] = 1b 		1.53 1.7
RSLEW-MODE = 24 kΩ
or MFR_SPEC_13[2:0] = 001b and MFR_SPEC_07[2] = 1b 		1.85 2.04
RSLEW-MODE = 30 kΩ
or MFR_SPEC_13[2:0] = 010b and MFR_SPEC_07[2] = 1b 		2.16 2.38
RSLEW-MODE = 39 kΩ
or MFR_SPEC_13[2:0] = 011b and MFR_SPEC_07[2] = 1b 		2.48 2.74
RSLEW-MODE = 56 kΩ
or MFR_SPEC_13[2:0] = 100b and MFR_SPEC_07[2] = 1b 		2.79 3.08
RSLEW-MODE = 75 kΩ
or MFR_SPEC_13[2:0] = 101b and MFR_SPEC_07[2] = 1b 		3.10 3.43
RSLEW-MODE = 100 kΩ
or MFR_SPEC_13[2:0] = 110b and MFR_SPEC_07[2] = 1b 		3.41 3.76
RSLEW-MODE ≥ 150 kΩ
or MFR_SPEC_13[2:0] = 111b and MFR_SPEC_07[2] = 1b 		3.73 4.13
MODE MODE bits set(1)
(M3M2M1M0)		 VSLEW-MODE ≤ 0.053 V with ±20 mV tolerance,
or MFR_SPEC_13[7:3] = 00x00		 0000
VSLEW-MODE = 0.159 V with ±20 mV tolerance,
MFR_SPEC_13[7:3] = 00x01b		 0001
VSLEW-MODE = 0.266 V with ±20 mV tolerance,
MFR_SPEC_13[7:3] = 00x10b		 0010
VSLEW-MODE = 0.372V with ±20 mV tolerance,
MFR_SPEC_13[7:3] = 00x11b		 0011
VSLEW-MODE = 0.478 V with ±20 mV tolerance,
MFR_SPEC_13[7:3] = 01x00b		 0100
VSLEW-MODE = 0.584V with ±20 mV tolerance,
MFR_SPEC_13[7:3] = 01x01b		 0101
VSLEW-MODE = 0.691 V with ±20 mV tolerance,
MFR_SPEC_13[7:3] = 01x10b		 0110
VSLEW-MODE = 0.797 V with ±20 mV tolerance,
MFR_SPEC_13[7:3] = 01x11b		 0111
VSLEW-MODE = 0.903 V with ±20 mV tolerance,
MFR_SPEC_13[7:3] = 10x00b		 1000
VSLEW-MODE = 1.009 V with ±20 mV tolerance,
MFR_SPEC_13[7:3] = 10x01b		 1001
VSLEW-MODE = 1.116 V with ±20 mV tolerance,
MFR_SPEC_13[7:3] = 10x10b		 1010
VSLEW-MODE = 1.222 V with ±20 mV tolerance,
MFR_SPEC_13[7:3] = 10x11b		 1011
VSLEW-MODE = 1.328 V with ±20 mV tolerance,
MFR_SPEC_13[7:3] = 11x00b		 1100
VSLEW-MODE = 1.434 V with ±20 mV tolerance,
MFR_SPEC_13[7:3] = 11x01b		 1101
VSLEW-MODE = 1.541 V with ±20 mV tolerance,
MFR_SPEC_13[7:3] = 11x10b		 1110
VSLEW-MODE = 1.615 V with ±10 mV tolerance,
MFR_SPEC_13[7:3] = 11x11b		 1111
O-USR PIN: OVERSHOOT AND UNDERSHOOT REDUCTION THRESHOLD SETTING
VOSR OSR voltage setting RO-USR ≤ 20 kΩ or MFR_SPEC_09 [2:0] = 000b 20 30 40 mV
RO-USR = 24 kΩ or MFR_SPEC_09 [2:0] = 001b 30 40 50
RO-USR = 30 kΩ or MFR_SPEC_09 [2:0] = 010b 50 60 70
RO-USR = 39 kΩ or MFR_SPEC_09 [2:0] = 011b 70 80 90
RO-USR = 56 kΩ or MFR_SPEC_09 [2:0] = 100b 90 100 110
RO-USR = 75 kΩ or MFR_SPEC_09 [2:0] = 101b 110 120 130
RO-USR = 100 kΩ or MFR_SPEC_09 [2:0] = 110b 130 140 150
RO-USR ≥ 150 kΩ or MFR_SPEC_09 [2:0] = 111b OFF
VUSR USR voltage setting VO-USR = 0.2 V with ±50 mV tolerance
or MFR_SPEC_09 [6:4] = 000b		 10 20 30 mV
VO-USR = 0.4 V with ±50 mV tolerance
or MFR_SPEC_09 [6:4] = 001b		 20 30 40
VO-USR = 0.6 V with ±50 mV tolerance
or MFR_SPEC_09 [6:4] = 010b		 50 60 70
VO-USR = 0.8 V with ±50 mV tolerance
or MFR_SPEC_09 [6:4] = 011b		 70 80 90
VO-USR = 1.0 V with ±50 mV tolerance
or MFR_SPEC_09 [6:4] = 100b		 90 100 110
VO-USR = 1.2 V with ±50 mV tolerance
or MFR_SPEC_09 [6:4] = 101b		 110 120 130
VO-USR = 1.4 V with ±50 mV tolerance
or MFR_SPEC_09 [6:4] = 110b		 130 140 150
1.55 V ≤ VO-USR ≤ 1.6 V
or MFR_SPEC_09 [6:4] = 111b		 OFF
VOSRHYS OSR voltage hysteresis(1) All settings 10 mV
VUSRHYS USR voltage hysteresis(1) All settings 10 mV
VBOOT PIN: BOOT VOLTAGE SETTING
VBOOT (1) BOOT voltage setting (B3B2B1) RVBOOT ≤ 20 kΩ, or MFR_SPEC_11 [3:1] = 000b 000
RVBOOT = 24 kΩ, or MFR_SPEC_11 [3:1] = 001b 001
RVBOOT = 30 kΩ, or MFR_SPEC_11 [3:1] = 010b 010
RVBOOT = 39 kΩ, or MFR_SPEC_11 [3:1] = 011b 011
RVBOOT = 56 kΩ, or MFR_SPEC_11 [3:1] = 100b 100
RVBOOT = 75 kΩ, or MFR_SPEC_11 [3:1] = 101b 101
RVBOOT = 100 kΩ, or MFR_SPEC_11 [3:1] = 110b 110
RVBOOT ≥ 150 kΩ, or MFR_SPEC_11 [3:1] = 111b 111
BOOT voltage setting (B7B6B5B4) VVBOOT ≤ 0.053 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0000b 0000
VVBOOT = 0.159 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0001b 0001
VVBOOT= 0.266 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0010b 0010
VVBOOT = 0.372 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0011b 0011
VVBOOT = 0.478 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0100b 0100
VVBOOT = 0.584 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0101b 0101
VVBOOT = 0.691 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0110b 0110
VVBOOT = 0.797 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 0111b 0111
VVBOOT = 0.903 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 1000b 1000
VVBOOT = 1.009 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 1001b 1001
VVBOOT = 1.116 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 1010b 1010
VVBOOT = 1.222 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 1011b 1011
VVBOOT = 1.328 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 1100b 1100
VVBOOT = 1.434 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 1101b 1101
VVBOOT = 1.541 V with ±20 mV tolerance, or MFR_SPEC_11 [7:4] = 1110b 1110
VVBOOT = 1.615 V with ±10 mV tolerance, or MFR_SPEC_11 [7:4] = 1111b 1111
PROTECTION: OVP, UVP, VR_RDY
VOVPFP Pre-bias OVP voltage threshold(1) ENABLE is low and VVSP > VOVPFP, PWM → LO 2.75 V
VOVPF5 Fixed OVP voltage threshold (VR12.5) ENABLE is high and (VVSP–VVSN) > VOVPH5 for 1 μs, PWM → LO,
VOUT(max) ≤ 1.8 V		 2.2 V
1.8 V < VOUT(max) ≤ 2.0 V 2.4
2.0 V < VOUT(max) ≤ 2.2 V 2.6
VOUT(max) > 2.2 V 2.8
VOVPF0 Fixed OVP voltage threshold (VR12.0) ENABLE is high and (VVSP–VVSN) > VOVPH5 for 1 μs, PWM → LO, 1.7 1.75 1.8
VOVPT5 Tracking OVP offset (VR12.5) Measured at the VSP pin w/r/t VID code, device latches OFF 340 375 405 mV
VOVPT0 Tracking OVP offset (VR12.0) Measured at the VSP pin w/r/t VID code, device latches OFF 200 225 250 mV
VRDYL VR_RDY low (UVP) threshold Measured at the VSP pin w/r/t VID code, device latches OFF 175 207 235 mV
tRDYDGLTO VR_RDY deglitch time Time from VSP out of overvoltage threshold to VR_RDY low 1 µs
tRDYDGLTU VR_RDY deglitch time Time from VSP out of undervoltage threshold to VR_RDY low, (ƒSW = 500 kHz) 32 µs
tHICCUP Hiccup delay after UVP and OCP 22 ms
TSEN PIN AND THERMAL SHUTDOWN: THERMAL VOLTAGE LEVELS
VTSEN Thermal voltage definition TJ = 90°C 1.32 V
TJ = 95°C 1.36
TJ = 100°C 1.4
TJ = 105°C 1.44
TJ = 110°C 1.48
TJ = 115°C 1.52
TJ = 120°C 1.56
TJ = 125°C 1.6
ITSEN TSEN current Leakage current –3 3 µA
OTPTHLD Over temperature protection threshold Based on the temperature measured on TSEN pin, default value 125 °C
OTPHYS Over temperature protection hysteresis 15 °C
PWM and SKIP-NVM OUTPUT: I/O VOLTAGE AND CURRENT°C
VPWML PWMx output low level ILOAD = -1 mA 0.15 0.3 V
VPWMH PWMx output high Level ILOAD = +1 mA 2.5 V
V SKIP-NVM_L SKIP-NVM output low Level ILOAD = –1 mA 0.15 0.3 V
V SKIP-NVM_H SKIP-NVM output high Level ILOAD = +1 mA 2.5 V
RP-S_UV PWMx//SKIP-NVM resistance(1) ENABLE = LOW, or UVLO 10 MΩ
DYNAMIC PHASE SHEDDING: THRESHOLDS
IDPSTHL Dynamic phase add/drop low threshold current MFR_SPEC_15 [3] = 0b N.A A
MFR_SPEC_15 [3] = 1b 10% × 4 × IOCLx
IDPSTHH Dynamic phase add/drop high threshold voltage MFR_SPEC_15 [2:0] = 000b 15% × 4 × IOCLx A
MFR_SPEC_15 [2:0] = 001b 20% × 4 × IOCLx
MFR_SPEC_15 [2:0] = 010b 25% × 4 × IOCLx
MFR_SPEC_15 [2:0] = 011b 30% × 4 × IOCLx
MFR_SPEC_15 [2:0] = 1xxb 35% × 4 × IOCLx
IDPSHYS Dynamic phase add/drop high hysteresis voltage Hysteresis 5% × 4 × IOCLx A
PROGRAMMABLE DROOP SETTING
DROOP Droop percentage settings MFR_SPEC_08 [7:0] = 00h 0 %
MFR_SPEC_08 [7:0] = 01h 25
MFR_SPEC_08 [7:0] = 02h 50
MFR_SPEC_08 [7:0] = 03h 75
MFR_SPEC_08 [7:0] = 04h (Default Setting) 100
MFR_SPEC_08 [7:0] = 10h 80
MFR_SPEC_08 [7:0] = 20h 85
MFR_SPEC_08 [7:0] = 30h 90
MFR_SPEC_08 [7:0] = 40h 95
MFR_SPEC_08 [7:0] = 50h 105
MFR_SPEC_08 [7:0] = 60h 110
MFR_SPEC_08 [7:0] = 70h 115
MFR_SPEC_08 [7:0] = 80h 120
MFR_SPEC_08 [7:0] = 90h 125
MFR_SPEC_08 [7:0] = A0h 150
SKIP-NVM PIN: PROGRAM MODE SETTING (NVM OR PINSTRAP)
PGRM Program mode for the configurations RSKIP-NVM ≤ 20 kΩ Pinstrap Program
Mode
RSKIP-NVM ≥ 100 kΩ NVM
IMON PIN: CURRENT MONITOR
IIMON4LK 0% IMAX level current output 4 phase, IMAX=80A, Σ iL = 0 A, RIMON=74.38kΩ 0 4 A
IIMON4LO 20% IMAX level current output 4 phase, IMAX=80A, Σ iL = 16 A, RIMON=74.38kΩ 13 16 18.5 A
IIMON4MID 100% IMAX level current output 4 phase, IMAX=80A, Σ iL = 80 A, RIMON=74.38kΩ 75 80 84 A
IIMON4HI 125% IMAX level current output 4 phase, IMAX=80A, Σ iL = 100 A, RIMON=74.38kΩ 94 100 105 A
VOUT MEASUREMENT: READ_VOUT
MVOUT(rng) VOUT measurement range 0.5 2.3 V
READ_VOUT accuracy 0.5 V ≤ VOUT < 0.7 V, VR12.0 mode -2 +2 VID
0.7V ≤ VOUT ≤ 1.0 V, VR12.0 mode -1 +1
1.0V < VOUT ≤ 1.52 V, VR12.0 mode -2 +2
0.5 V ≤ VOUT ≤ 2.3 V, VR12.5 mode -1 +1
MFR_READ_VOUT accuracy 0.5 V ≤ VOUT < 0.7 V, VR12.0 mode -12.5 12.5 mV
0.7V ≤ VOUT ≤ 1.0 V, VR12.0 mode -7.5 7.5
1.0V < VOUT ≤ 1.52 V, VR12.0 mode -10 10
0.5 V ≤ VOUT ≤ 2.3 V, VR12.5 mode -12.5 12.5
(1) Specified by design. Not production tested.

6.6 I/O Timing Requirements

MIN TYP MAX UNIT
tSTARTUP1 Startup time VBOOT> 0 V, no faults, time from V3R3 high to VOUT ramp, CVREF = 1 µF 1.2 ms
tSTARTUP2 Startup time VBOOT> 0 V, no faults, time from V3R3 high until the controller responds to PMBus commands, CVREF = 1 µF 1.5 ms
tRDY_POD VR_RDY power-on-delay time(1) DAC settled to VR_RDY going high 1 ms
tOFF_MIN Controller minimum OFF time(1) Fixed value 20 50 80 ns
tEN_RDY ENABLE low to VR_RDY low 20 100 ns
tRDY_VSP VR_RDY low to VSP change(1) 100 ns
(1) Specified by design. Not production tested.

6.7 Switching Characteristics

TA = 25°C. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
F-IMAX PIN: FREQUENCY
fSW Switching frequency VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 20 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0000b		 270 300 330 kHz
VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 24 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0001b		 360 400 440
VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 30 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0010b		 450 500 550
VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 39 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0011b		 540 600 660
VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 56 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0100b		 630 700 770
VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 75 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0101b		 720 800 880
VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 100 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0110b		 810 900 990
VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 150 kΩ and MFR_SPEC_12[7] = 0b ; or MFR_SPEC_12[7:4] = 0111b		 900 1000 1100
VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 20 kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1000b		 315 350 385
VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 24 kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1001b		 405 450 495
VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 30 kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1010b		 495 550 605
VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 39 kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1011b		 585 650 715
VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 56 kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1100b		 675 750 825
VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 75 kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1101b		 765 850 935
VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 100 kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1110b		 855 950 1045
VVIN = 12 V, VVSP = 1.7 V
RF-IMAX = 150kΩ and MFR_SPEC_12[7] = 1b ; or MFR_SPEC_12[7:4] = 1111b		 900 1000 1100

6.8 Typical Characteristics

TPS53647 D001_slusc39.gif Figure 1. VIN Supply Current vs Junction Temperature
TPS53647 D004_slusc39.gif
VUVLO = 7.25 V
Figure 3. VIN UVLO Voltage vs Junction Temperature
TPS53647 D009_slusc39.gif
Figure 5. Reference Voltage vs Junction Temperature
TPS53647 D002_slusc39.gif Figure 2. V5 Supply Current vs Junction Temperature
TPS53647 D003_slusc39.gif
Figure 4. V5 UVLO Voltage vs Junction Temperature
TPS53647 D010_slusc39.gif
ILOAD = 5 mA
Figure 6. V3R3 Load Regulation vs Junction Temperature

 
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