The TPS54040A device is a 42 V, 0.5 A, step down regulator with an integrated high side MOSFET. Current mode control provides simple external compensation and flexible component selection. A low ripple pulse skip mode reduces the no load, regulated input supply current to 116 μA. Using the enable pin, shutdown supply current is nominally 1.3 μA when the enable pin is low.
Under voltage lockout is internally set at 2.5 V, but can be increased using the enable pin. The output voltage startup ramp is controlled by the slow start pin that can also be configured for sequencing or tracking. An open drain power good signal indicates when the output is within 94% to 107% of its nominal voltage.
A wide switching frequency range allows efficiency and external component size to be optimized. Frequency fold back and thermal shutdown protects the part during an overload condition.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS54040A | MSOP-PowerPAD (10) | 3.00 mm × 3.00 mm |
VSON (10) | 3.00 mm × 3.00 mm |
SPACER
Changes from A Revision (January 2014) to B Revision
Changes from * Revision (March 2012) to A Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NO. | NAME | |||
1 | BOOT | O | A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. | |
8 | COMP | O | Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. | |
3 | EN | I | Enable pin, internal pull-up current source. Pull below 1.2V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. | |
9 | GND | — | Ground | |
10 | PH | I | The source of the internal high-side power MOSFET. | |
6 | PWRGD | O | An open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or EN shut down. | |
5 | RT/CLK | I | Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor set function. | |
4 | SS/TR | I | Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. | |
2 | VIN | I | Input supply voltage, 3.5 V to 42 V. | |
7 | VSENSE | I | Inverting input of the transconductance (gm) error amplifier. | |
11 | Thermal Pad | — | GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. |