DATA SHEET
TPS54325 4.5-V to 18-V, 3-A Output Synchronous Step Down Switcher with Integrated FET
1 Features
- D-CAP2™ Mode Enables Fast Transient Response
- Low Output Ripple and Allows Ceramic Output Capacitor
- Wide VCC Input Voltage Range: 4.5 V to 18 V
- Wide VIN Input Voltage Range: 2.0 V to 18 V
- Output Voltage Range: 0.76 V to 5.5 V
- Highly Efficient Integrated FET’s Optimized for Lower Duty Cycle Applications – 120 mΩ (High Side) and 70 mΩ (Low Side)
- High Efficiency, less than 10 μA at shutdown
- High Initial Bandgap Reference Accuracy
- Adjustable Soft Start
- Pre-Biased Soft Start
- 700-kHz Switching Frequency (fSW)
- Cycle By Cycle Over Current Limit
- Power Good Output
2 Applications
- Wide Range of Applications for Low Voltage System
- Digital TV Power Supply
- High Definition Blu-ray Disc™ Players
- Networking Home Terminal
- Digital Set Top Box (STB)
3 Description
The TPS54325 device is an adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54325 device enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution.
The main control loop for the TPS54325 uses the D-CAP2™ mode control which provides a very fast transient response with no external components. The TPS54325 also has a proprietary circuit that enables the device to adapt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VCC input , and from 2.0-V to 18-V VIN input power supply voltage. The output voltage can be programmed between 0.76 V and 5.5 V. The device also features an adjustable slow start time and a power good function. The TPS54325 is available in the 14 pin HTSSOP package, and designed to operate from –40°C to 85°C.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| TPS54325 | HTSSOP (14) | 5.00 mm × 4.40 mm |
- For all available packages, see the orderable addendum at the end of the datasheet.
4 Simplified Schematic
Load Transient Response
5 Revision History
Changes from E Revision (January 2014) to F Revision
- Added, updated, or renamed the following sections: Device Information Table, Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering InformationGo
Changes from D Revision (January 2012) to E Revision
- Changed text in the Bootstrap Capacitor Selection from "between the VREG5 to GND pin for proper operation" to "between the VBST to SW pin for proper operationGo
Changes from C Revision (July 2011) to D Revision
Changes from B Revision (March 2011) to C Revision
- Changed EN high-level input voltage from min of 2.0 V to min of 1.6 VGo
- Changed EN low-level input voltage from max of 0.48 V to max of 0.4 VGo
Changes from * Revision (May 2009) to A Revision
- Changed TA, for the current limit, Iocl, From: 25°C to –40°C To: 85°C and 3.5 A was added at the MIN valueGo
6 Pin Configuration and Functions
14-Pin
PWP PACKAGE
Top View
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| VO | 1 | I | Connect to output of converter. This terminal is used for On-Time Adjustment. |
| VFB | 2 | I | Converter feedback input. Connect with feedback resistor divider. |
| VREG5 | 3 | O | 5.5 V power supply output. A capacitor (typical 1μF) should be connected to GND. |
| SS | 4 | I | Soft-start control. A external capacitor should be connected to GND. |
| GND | 5 | –– | Signal ground pin |
| PG | 6 | O | Open drain power good output |
| EN | 7 | I | Enable control input |
| PGND1, PGND2 | 8, 9 | –– | Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND and GND strongly together near the IC. |
| SW1, SW2 | 10, 11 | O | Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current comparators. |
| VBST | 12 | O | Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin. |
| VIN | 13 | I | Power input and connected to high side NFET drain |
| VCC | 14 | I | Supply input for 5 V internal linear regulator for the control circuitry |
| PowerPAD™ | –– | –– | Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected to PGND. |
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| VI | Input voltage range | VIN, VCC, EN | –0.3 | 20 | V |
| VBST | –0.3 | 26 | V | ||
| VBST (vs SW1, SW2) | –0.3 | 6.5 | V | ||
| VFB, VO, SS, PG | –0.3 | 6.5 | V | ||
| SW1, SW2 | –2 | 20 | V | ||
| SW1, SW2 (10 ns transient) | –3 | 20 | V | ||
| VO | Output voltage range | VREG5 | –0.3 | 6.5 | V |
| PGND1, PGND2 | –0.3 | 0.3 | V | ||
| Vdiff | Voltage from GND to POWERPAD | –0.2 | 0.2 | V | |
| TJ | Operating junction temperature | –40 | 150 | °C | |
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| Tstg | Storage temperature range | –55 | 150 | °C | |
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | 2000 | V | |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | 500 | ||||
(1) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Thermal Information
| THERMAL METRIC(1) | PWP | UNIT | |
|---|---|---|---|
| 12 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 55.6 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 51.3 | |
| RθJB | Junction-to-board thermal resistance | 26.4 | |
| ψJT | Junction-to-top characterization parameter | 1.8 | |
| ψJB | Junction-to-board characterization parameter | 20.6 | |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 4.3 | |
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| VCC | Supply input voltage range | 4.5 | 18 | V | |
| VIN | Power input voltage range | 2 | 18 | V | |
| VI | Input voltage range | VBST | –0.1 | 24 | V |
| VBST (vs SW1, SW2) | –0.1 | 6 | |||
| SS, PG | –0.1 | 6 | |||
| EN | –0.1 | 18 | |||
| VO, VFB | –0.1 | 5.5 | |||
| SW1, SW2 | –1.8 | 18 | |||
| SW1, SW2 (10 ns transient) | –3 | 18 | |||
| PGND1, PGND2 | –0.1 | 0.1 | |||
| VO | Output voltage range | VREG5 | –0.1 | 6 | V |
| IO | Output current range | IVREG5 | 0 | 10 | mA |
| TA | Operating free-air temperature | –40 | 85 | °C | |
| TJ | Operating junction temperature | –40 | 125 | °C | |
7.5 Electrical Characteristics
over operating free-air temperature range, VCC, VIN = 12 V (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY CURRENT | ||||||
| IVCC | Operating - non-switching supply current | VCC current, TA = 25°C, EN = 5 V, VFB = 0.8 V |
850 | 1300 | μA | |
| IVCCSDN | Shutdown supply current | VCC current, TA = 25°C, EN = 0 V | 10 | μA | ||
| LOGIC THRESHOLD | ||||||
| VENH | EN high-level input voltage | EN | 1.6 | V | ||
| VENL | EN low-level input voltage | EN | 0.4 | V | ||
| VFB VOLTAGE AND DISCHARGE RESISTANCE | ||||||
| VFBTH | VFB threshold voltage | TA = 25°C, VO = 1.05 V | 757 | 765 | 773 | mV |
| TA = 0°C to 85°C, VO = 1.05 V(1) | 753 | 777 | ||||
| TA = -40°C to 85°C, VO = 1.05 V(1) | 751 | 779 | ||||
| IVFB | VFB input current | VFB = 0.8 V, TA = 25°C | 0 | ±0.1 | μA | |
| RDischg | VO discharge resistance | EN = 0 V, VO = 0.5 V, TA = 25°C | 50 | 100 | Ω | |
| VREG5 OUTPUT | ||||||
| VVREG5 | VREG5 output voltage | TA = 25°C, 6.0 V < VCC < 18 V, 0 < IVREG5 < 5 mA |
5.3 | 5.5 | 5.7 | V |
| VLN5 | Line regulation | 6.0 V < VCC < 18 V, IVREG5 = 5 mA | 20 | mV | ||
| VLD5 | Load regulation | 0 mA < IVREG5 < 5 mA | 100 | mV | ||
| IVREG5 | Output current | VCC = 6 V, VREG5 = 4.0 V, TA = 25°C | 70 | mA | ||
| MOSFET | ||||||
| Rdsonh | High side switch resistance | 25°C, VBST - SW1, SW2 = 5.5 V | 120 | mΩ | ||
| Rdsonl | Low side switch resistance | 25°C | 70 | mΩ | ||
| CURRENT LIMIT | ||||||
| Iocl | Current limit | TA = –40°C to 85°C (1) | 3.5 | 4.1 | 5.5 | A |
| THERMAL SHUTDOWN | ||||||
| TSDN | Thermal shutdown threshold | Shutdown temperature (1) | 150 | °C | ||
| Hysteresis (1) | 25 | |||||
| ON-TIME TIMER CONTROL | ||||||
| tON | On time | VIN = 12 V, VO = 1.05 V | 145 | ns | ||
| tOFF(MIN) | Minimum off time | TA = 25°C, VFB = 0.7 V | 260 | ns | ||
| SOFT START | ||||||
| ISSC | SS charge current | VSS = 0 V | 1.4 | 2.0 | 2.6 | μA |
| ISSD | SS discharge current | VSS = 0.5 V | 0.1 | 0.2 | mA | |
| POWER GOOD | ||||||
| VTHPG | PG threshold | VFB rising (good) | 85% | 90% | 95% | |
| VFB falling (fault) | 85% | |||||
| IPG | PG sink current | PG = 0.5 V | 2.5 | 5 | mA | |
| OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION | ||||||
| VOVP | Output OVP trip threshold | OVP detect | 115% | 120% | 125% | |
| TOVPDEL | Output OVP prop delay | 5 | μs | |||
| VUVP | Output UVP trip threshold | UVP detect | 65% | 70% | 75% | |
| Hysteresis | 10% | |||||
| TUVPDEL | Output UVP delay | 0.25 | ms | |||
| TUVPEN | Output UVP enable delay | Relative to soft-start time | x 1.7 | |||
| UVLO | ||||||
| VUVLO | UVLO threshold | Wake up VREG5 voltage | 3.45 | 3.70 | 3.95 | V |
| Hysteresis VREG5 voltage | 0.15 | 0.25 | 0.35 | |||
(1) Not production tested.
