The TPS54427 is an adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54427 enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution.
The main control loop for the TPS54427 uses the D-CAP2™ mode control which provides a fast transient response with no external compensation components.
The TPS54427 also has a proprietary circuit that enables the device to adopt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors.
The device operates from 4.5-V to 18-V VIN input. The output voltage can be programmed between
0.76 V and 7 V.
The device also features an adjustable soft start time.
The TPS54427 is available in the 8-pin DDA package and 10-pin DRC, and is designed to operate from –40°C to 85°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS54427 | SO PowerPAD™ (8) | 4.89 mm × 3.90 mm |
VSON (10) | 3.00 mm × 3.00 mm |
Changes from B Revision (October 2015) to C Revision
Changes from A Revision (June 2013) to B Revision
Changes from * Revision (November 2011) to A Revision
PIN | DESCRIPTION | ||
---|---|---|---|
NAME | DDA | DRC | |
EN | 1 | 1 | Enable input control. Active high and must be pulled up to enable the device. |
VFB | 2 | 2 | Converter feedback input. Connect to output voltage with feedback resistor divider. |
VREG5 | 3 | 3 | 5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not active when EN is low. |
SS | 4 | 4 | Soft-start control. An external capacitor should be connected to GND. |
GND | 5 | 5 | Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at a single point. |
SW | 6 | 6, 7 | Switch node connection between high-side NFET and low-side NFET. |
VBST | 7 | 8 | Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between VBST and SW pins. An internal diode is connected between VREG5 and VBST. |
VIN | 8 | 9, 10 | Input voltage supply pin. |
Exposed Thermal Pad | Back side | Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to GND. | |
Back side | Thermal pad of the package. PGND power ground return of internal low-side FET. Must be soldered to achieve appropriate dissipation. |