The TPS54427 is an adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54427 enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution.
The main control loop for the TPS54427 uses the D-CAP2™ mode control which provides a fast transient response with no external compensation components.
The TPS54427 also has a proprietary circuit that enables the device to adopt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors.
The device operates from 4.5-V to 18-V VIN input. The output voltage can be programmed between
0.76 V and 7 V.
The device also features an adjustable soft start time.
The TPS54427 is available in the 8-pin DDA package and 10-pin DRC, and is designed to operate from –40°C to 85°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS54427 | SO PowerPAD™ (8) | 4.89 mm × 3.90 mm |
VSON (10) | 3.00 mm × 3.00 mm |
Changes from B Revision (October 2015) to C Revision
Changes from A Revision (June 2013) to B Revision
Changes from * Revision (November 2011) to A Revision
PIN | DESCRIPTION | ||
---|---|---|---|
NAME | DDA | DRC | |
EN | 1 | 1 | Enable input control. Active high and must be pulled up to enable the device. |
VFB | 2 | 2 | Converter feedback input. Connect to output voltage with feedback resistor divider. |
VREG5 | 3 | 3 | 5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not active when EN is low. |
SS | 4 | 4 | Soft-start control. An external capacitor should be connected to GND. |
GND | 5 | 5 | Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at a single point. |
SW | 6 | 6, 7 | Switch node connection between high-side NFET and low-side NFET. |
VBST | 7 | 8 | Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between VBST and SW pins. An internal diode is connected between VREG5 and VBST. |
VIN | 8 | 9, 10 | Input voltage supply pin. |
Exposed Thermal Pad | Back side | Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to GND. | |
Back side | Thermal pad of the package. PGND power ground return of internal low-side FET. Must be soldered to achieve appropriate dissipation. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VIN, EN | –0.3 | 20 | V |
VBST | –0.3 | 26 | V | |
VBST (10 ns transient) | –0.3 | 28 | V | |
VBST (vs SW) | –0.3 | 6.5 | V | |
VFB, SS | –0.3 | 6.5 | V | |
SW | –2 | 20 | V | |
SW (10 ns transient) | –3 | 22 | V | |
Output voltage | VREG5 | –0.3 | 6.5 | V |
GND | –0.3 | 0.3 | V | |
Voltage from GND to thermal pad, Vdiff | –0.2 | 0.2 | V | |
Operating junction temperature, TJ | –40 | 150 | °C | |
Storage temperature, Tstg | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
THERMAL METRIC(1) | TPS54427 | UNIT | ||
---|---|---|---|---|
DDA [SO PowerPAD] | DRC [VSON] | |||
8 PINS | 10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 42.1 | 43.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 50.9 | 53.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 31.8 | 18.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 5 | 0.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 13.5 | 18.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 7.1 | 4.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY CURRENT | ||||||
IVIN | Operating - non-switching supply current | VIN current, TA = 25°C, EN = 5 V, VFB = 0.8 V |
950 | 1400 | μA | |
IVINSDN | Shutdown supply current | VIN current, TA = 25°C, EN = 0 V | 3.0 | 10 | μA | |
LOGIC THRESHOLD | ||||||
VENH | EN high-level input voltage | EN | 1.6 | V | ||
VENL | EN low-level input voltage | EN | 0.6 | V | ||
REN | EN pin resistance to GND | VEN = 12 V | 225 | 450 | 900 | kΩ |
VFB VOLTAGE AND DISCHARGE RESISTANCE | ||||||
VFBTH | VFB threshold voltage | TA = 25°C, VO = 1.05 V, continuous mode mode | 757 | 765 | 773 | mV |
TA = –40°C to 85°C, VO = 1.05 V, continuous mode mode(1) |
751 | 765 | 779 | |||
IVFB | VFB input current | VFB = 0.8 V, TA = 25°C | 0 | ±0.1 | μA | |
VREG5 OUTPUT | ||||||
VVREG5 | VREG5 output voltage | TA = 25°C, 6.0 V < VIN < 18 V, 0 < IVREG5 < 5 mA |
5.2 | 5.5 | 5.7 | V |
VLN5 | Line regulation | 6 V < VIN < 18 V, IVREG5 = 5 mA | 25 | mV | ||
VLD5 | Load regulation | 0 mA < IVREG5 < 5 mA | 100 | mV | ||
IVREG5 | Output current | VIN = 6 V, VREG5 = 4.0 V, TA = 25°C | 60 | mA | ||
MOSFET | ||||||
RDS(on)h | High side switch resistance (DDA) | 25°C, VBST - SW = 5.5 V | 70 | mΩ | ||
High side switch resistance (DRC) | 74 | |||||
RDS(on)l | Low side switch resistance | 25°C | 53 | mΩ | ||
CURRENT LIMIT | ||||||
Iocl | Current limit | L out = 1.5 µH (1) | 4.6 | 5.3 | 6.8 | A |
THERMAL SHUTDOWN | ||||||
TSDN | Thermal shutdown threshold | Shutdown temperature(1) | 170 | °C | ||
Hysteresis(1) | 35 | |||||
ON-TIME TIMER CONTROL | ||||||
tON | On time | VIN = 12 V, VO = 1.05 V | 150 | ns | ||
tOFF(MIN) | Minimum off time | TA = 25°C, VFB = 0.7 V | 260 | 310 | ns | |
SOFT START | ||||||
ISSC | SS charge current | VSS = 1 V | 4.2 | 6.0 | 7.8 | μA |
ISSD | SS discharge current | VSS = 0.5 V | 0.1 | 0.2 | mA | |
UVLO | ||||||
UVLO | UVLO threshold | Wake up VREG5 voltage | 3.45 | 3.75 | 4.05 | V |
Hysteresis VREG5 voltage | 0.19 | 0.32 | 0.45 |
The TPS54427 is a 4-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer types.
The main control loop of the TPS54427 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2™ mode control.
TPS54427 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS54427 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
The soft start function is adjustable. When the EN pin becomes high, 6-uA current begins charging the capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is 6-µA.
The TPS54427 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation.
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin, Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current IOUT. The TPS54427 constantly monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time. If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the higher value.
There are some important considerations for this type of over-current protection. The load current one half of the peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output voltage to fall. When the over current condition is removed, the output voltage will return to the regulated value. This protection is non-latching.
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower than UVLO threshold voltage, the TPS54427 is shut off. This protection is non-latching.
TPS54427 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 170°C), the device is shut off. This is non-latch protection.
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the TPS54427 operates in normal switching mode. Normal continuous conduction mode(CCM) occurs when the minimum switch current is above 0 A. In CM the TPS54427 operates at a quasi-fixed frequency of 650 kHz.
When the TPS54427 is in normal CCM operating mode and switch current falls below 0 A, the device begins operating in forced CCM.