Refer to the PDF data sheet for device specific package drawings
The TPS54620 in thermally enhanced 3.50 mm × 3.50 mm QFN package is a full featured 17-V, 6-A, synchronous, step-down converter which is optimized for small designs through high efficiency and integrating the high-side and low-side MOSFETs. Further space savings are achieved through current mode control, which reduces component count, and by selecting a high switching frequency, reducing the footprint of the inductor.
The output voltage start-up ramp is controlled by the SS/TR pin which allows operation as either a stand-alone power supply or in tracking situations. Power sequencing is also possible by correctly configuring the enable and the open-drain power good pins.
Cycle-by-cycle current limiting on the high-side FET protects the device in overload situations and is enhanced by a low-side sourcing current limit which prevents current runaway. There is also a low-side sinking current limit that turns off the low-side MOSFET to prevent excessive reverse current. Thermal shutdown disables the part when die temperature exceeds thermal shutdown temperature.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS54620 | VQFN (14) | 3.50 mm × 3.50 mm |
Changes from E Revision (June 2016) to F Revision
Changes from D Revision (October 2014) to E Revision
Changes from C Revision (April 2011) to D Revision
Changes from B Revision (October 2010) to C Revision
Changes from A Revision (January 2010) to B Revision
Changes from * Revision (May 2009) to A Revision
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
RT/CLK | 1 | I | Automatically selects between RT mode and CLK mode. An external timing resistor adjusts the switching frequency of the device; in CLK mode, the device synchronizes to an external clock. |
GND | 2, 3 | G | Return for control circuitry and low-side power MOSFET. |
PVIN | 4, 5 | P | Power input. Supplies the power switches of the power converter. |
VIN | 6 | P | Supplies the control circuitry of the power converter. |
VSENSE | 7 | I | Inverting input of the gm error amplifier. |
COMP | 8 | O | Error amplifier output, and input to the output switch current comparator. Connect frequency compensation to this pin. |
SS/TR | 9 | O | Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing. |
EN | 10 | I | Enable pin. Float to enable. Adjust the input undervoltage lockout with two resistors. |
PH | 11, 12 | O | Switch node. |
BOOT | 13 | I | A bootstrap cap is required between BOOT and PH. The voltage on this cap carries the gate drive voltage for the high-side MOSFET. |
PWRGD | 14 | G | Power Good fault pin. Asserts low if output voltage is low because of thermal shutdown, dropout, over-voltage, EN shutdown, or during slow start. |
Exposed Thermal PAD | 15 | G | Thermal pad of the package and signal ground and it must be soldered down for proper operation. |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | Input voltage | 4.5 | 17 | V | |
PVIN | Power stage input voltage | 1.6 | 17 | V | |
Output current | 0 | 6 | A | ||
TJ | Operating junction temperature | –40 | 150 | °C |
THERMAL METRIC(1) | TPS54620 | UNIT | ||
---|---|---|---|---|
RGY (VQFN) | RHL (VQFN) | |||
14 PINS | 14 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 40.1 | 40.1 | °C/W |
RθJCtop | Junction-to-case (top) thermal resistance | 34.4 | 34.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 11.4 | 11.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.5 | 0.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 11.4 | 11.4 | °C/W |
RθJCbot | Junction-to-case (bottom) thermal resistance | 1.8 | 1.8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
SUPPLY VOLTAGE (VIN AND PVIN PINS) | |||||
PVIN operating input voltage | 1.6 | 17 | V | ||
VIN operating input voltage | 4.5 | 17 | V | ||
VIN internal UVLO threshold | VIN rising | 4 | 4.5 | V | |
VIN internal UVLO hysteresis | 150 | mV | |||
VIN shutdown supply Current | EN = 0 V | 2 | 5 | μA | |
VIN operating—nonswitching supply current | VSENSE = 810 mV | 600 | 800 | μA | |
ENABLE AND UVLO (EN PIN) | |||||
Enable threshold | Rising | 1.21 | 1.26 | V | |
Enable threshold | Falling | 1.10 | 1.17 | V | |
Input current | EN = 1.1 V | 1.15 | μA | ||
Hysteresis current | EN = 1.3 V | 3.4 | μA | ||
VOLTAGE REFERENCE | |||||
Voltage reference | 0 A ≤ IOUT ≤ 6 A | 0.792 | 0.8 | 0.808 | V |
MOSFET | |||||
High-side switch resistance | BOOT-PH = 3 V | 32 | 60 | mΩ | |
High-side switch resistance(1) | BOOT-PH = 6 V | 26 | 40 | mΩ | |
Low-side Switch Resistance(1) | VIN = 12 V | 19 | 30 | mΩ | |
ERROR AMPLIFIER | |||||
Error amplifier Transconductance (gm) | –2 μA < ICOMP < 2 μA, V(COMP) = 1 V | 1300 | μMhos | ||
Error amplifier DC gain | VSENSE = 0.8 V | 1000 | 3100 | V/V | |
Error amplifier source/sink | V(COMP) = 1 V, 100-mV input overdrive | ±110 | μA | ||
Start switching threshold | 0.25 | V | |||
COMP to Iswitch gm | 16 | A/V | |||
CURRENT LIMIT | |||||
High-side switch current limit threshold | 8 | 11 | A | ||
Low-side switch sourcing current limit | 7 | 10 | A | ||
Low-side switch sinking current limit | 2.3 | A | |||
THERMAL SHUTDOWN | |||||
Thermal shutdown | 160 | 175 | °C | ||
Thermal shutdown hysteresis | 10 | °C | |||
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) | |||||
Minimum switching frequency | Rrt = 240 kΩ (1%) | 160 | 200 | 240 | kHz |
Switching frequency | Rrt = 100 kΩ (1%) | 400 | 480 | 560 | kHz |
Maximum switching frequency | Rrt = 29 kΩ (1%) | 1440 | 1600 | 1760 | kHz |
Minimum pulse width | 20 | ns | |||
RT/CLK high threshold | 2 | V | |||
RT/CLK low threshold | 0.8 | V | |||
RT/CLK falling edge to PH rising edge delay | Measured at 500 kHz with RT resistor in series | 66 | ns | ||
Switching frequency range (RT mode set point and PLL mode) | 200 | 1600 | kHz | ||
PH (PH PIN) | |||||
Minimum on-time | Measured at 90% to 90% of VIN, 25°C, IPH = 2 A | 94 | 135 | ns | |
Minimum off-time | BOOT-PH ≥ 3 V | 0 | ns | ||
BOOT (BOOT PIN) | |||||
BOOT-PH UVLO | 2.1 | 3 | V | ||
SLOW START AND TRACKING (SS/TR PIN) | |||||
SS charge current | 2.3 | μA | |||
SS/TR to VSENSE matching | V(SS/TR) = 0.4 V | 29 | 60 | mV | |
POWER GOOD (PWRGD PIN) | |||||
VSENSE threshold | VSENSE falling (Fault) | 91 | % Vref | ||
VSENSE rising (Good) | 94 | % Vref | |||
VSENSE rising (Fault) | 109 | % Vref | |||
VSENSE falling (Good) | 106 | % Vref | |||
Output high leakage | VSENSE = Vref, V(PWRGD) = 5.5 V | 30 | 100 | nA | |
Output low | I(PWRGD) = 2 mA | 0.3 | V | ||
Minimum VIN for valid output | V(PWRGD) < 0.5 V at 100 μA | 0.6 | 1 | V | |
Minimum SS/TR voltage for PWRGD | 1.4 | V |