TPS54821 4.5 V to 17 V Input, 8 A Synchronous Step Down Converter With Hiccup

1 Features

Integrated 26 mΩ / 19 mΩ MOSFETs
Split Power Rail: 1.6 V to 17 V on PVIN
200 kHz to 1.6 MHz Switching Frequency
Synchronizes to External Clock
0.6V ±1% Voltage Reference Over Temperature
Low 2 µA Shutdown Quiescent Current
Monotonic Start-Up into Pre-biased Outputs
Adjustable Slow Start/Power Sequencing
Power Good Output Monitor for Undervoltage and Overvoltage
Adjustable Input Undervoltage Lockout
Software Tools Available

2 Applications

Digital TV Power Supplies
Set Top Boxes
Blu-ray DVDs
Home Terminals
High Performance Point of Load Regulation

3 Description

The TPS54821 in thermally enhanced 3.5 mm x 3.5 mm QFN package is a full featured 17 V, 8 A synchronous step down converter which is optimized for small designs through high efficiency and integrating the high-side and low-side MOSFETs. Further space savings are achieved through current mode control, which reduces component count, and by selecting a high switching frequency, reducing the inductor's footprint.

The output voltage startup ramp is controlled by the SS/TR pin which allows operation as either a stand alone power supply or in tracking situations. Power sequencing is also possible by correctly configuring the enable and the open drain power good pins.

Cycle by cycle current limiting on the high-side FET protects the device in overload situations and is enhanced by a low-side sourcing current limit which prevents current runaway. There is also a low-side sinking current limit which turns off the low-side MOSFET to prevent excessive reverse current. Hiccup protection will be triggered if the overcurrent condition has persisted for longer than the preset time. Thermal hiccup protection disables the device when the die temperature exceeds the thermal shutdown temperature and enables the part again after the built-in thermal shutdown hiccup time.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS54821	VQFN (14)	3.50 mm x 3.50 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

Efficiency, V_OUT = 3.3 V, F_SW = 480 kHz

4 Revision History

Changes from A Revision (November 2014) to B Revision

Deleted SWIFT™ from the data sheet title Go
Deleted Features: For SWIFT™ Documentation visit http://www.ti.com/swiftGo
Moved Storage temperature to the Absolute Maximum RatingsGo
Changed Handling Ratings to ESD Ratings Go

Changes from * Revision (October 2011) to A Revision

Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Go
Deleted Feature: –40°C to 125°C Operating Junction Temperature Range Go
Added the I/O column to the Pin Functions table Go
Added I_OUT = 8A and I_OUT = 6A to the Operating Junction Temperature row of the ABS MAX table, also Min = -40 and Max =150 Go

5 Pin Configuration and Functions

RHL Package

14 Pins

(Top View)

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
RT/CLK	1	I	Automatically selects between RT mode and CLK mode. An external timing resistor adjusts the switching frequency of the device; In CLK mode, the device synchronizes to an external clock.
GND	2, 3	-	Return for control circuitry and low-side power MOSFET.
PVIN	4, 5	I	Power input. Supplies the power switches of the power converter.
VIN	6	I	Supplies the control circuitry of the power converter.
VSENSE	7	I	Inverting input of the gm error amplifier.
COMP	8	I	Error amplifier output, and input to the output switch current comparator. Connect frequency compensation to this pin.
SS/TR	9	I	Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing.
EN	10	I	Enable pin. Float to enable. Adjust the input undervoltage lockout with two resistors.
PH	11, 12	O	The switch node.
BOOT	13	O	A bootstrap cap is required between BOOT and PH. The voltage on this cap carries the gate drive voltage for the high-side MOSFET.
PWRGD	14	O	Power Good fault pin. Asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage, EN shutdown or during slow start.
Exposed Thermal PAD	15	-	Thermal pad of the package and signal ground and it must be soldered down for proper operation.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Input Voltage	VIN	–0.3	20	V
	PVIN	–0.3	20
	EN	–0.3	6
	BOOT	–0.3	27
	VSENSE	–0.3	3
	COMP	–0.3	3
	PWRGD	–0.3	6
	SS/TR	–0.3	3
	RT/CLK	–0.3	6
Output Voltage	BOOT-PH	0	7.5	V
	PH	–1	20
	PH 10ns Transient	–3	20
Vdiff (GND to exposed thermal pad)		–0.2	0.2	V
Source Current	RT/CLK		±100	µA
Source Current	PH		Current Limit	A
Sink Current	PH		Current Limit	A
	PVIN		Current Limit	A
	COMP		±200	µA
	PWRGD	–0.1	5	mA
Operating Junction Temperature	I_OUT = 8 A	–40	125	°C
Operating Junction Temperature	I_OUT = 6 A	–40	150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Input voltage range	VIN	4.5	17	V
Power stage input voltage range	PVIN	1.6	17	V
Output current	T_J = –40°C to 125°C	0	8	A
Operating junction temperature, T_J	I_OUT = 6 A	–40	150	°C
Operating junction temperature, T_J	I_OUT = 8 A	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾		TPS54821	UNITS
THERMAL METRIC⁽¹⁾⁽²⁾		RHL (14 PINS)	UNITS
R_θJA	Junction-to-ambient thermal resistance	47.2	°C/W
R_θJA	Junction-to-ambient thermal resistance⁽³⁾	32
R_θJCtop	Junction-to-case (top) thermal resistance	64.8
R_θJB	Junction-to-board thermal resistance	14.4
ψ_JT	Junction-to-top characterization parameter	0.5
ψ_JB	Junction-to-board characterization parameter	14.7
R_θJCbot	Junction-to-case (bottom) thermal resistance	3.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) Power rating at a specific ambient temperature T_A should be determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more information.

(3) Test board conditions:

2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch
2 oz. copper traces located on the top of the PCB
2 oz. copper ground planes on the 2 internal layers and bottom layer
4 0.010 inch thermal vias located under the device package

6.5 Electrical Characteristics

T_J = –40°C to 125°C, VIN = 4.5V to 17V, PVIN = 1.6V to 17V (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE (VIN AND PVIN PINS)
PVIN operating input voltage		1.6		17	V
VIN operating input voltage		4.5		17	V
VIN internal UVLO threshold	VIN rising		4.0	4.5	V
VIN internal UVLO hysteresis			150		mV
VIN shutdown supply Current	EN = 0 V		2	5	μA
VIN operating – non switching supply current	VSENSE = 610 mV		600	800	μA
ENABLE AND UVLO (EN PIN)
Enable threshold	Rising		1.21	1.26	V
Enable threshold	Falling	1.10	1.17
Input current	EN = 1.1 V		1.15		μA
Hysteresis current	EN = 1.3 V		3.3		μA
VOLTAGE REFERENCE
Voltage reference	0 A ≤ I_OUT ≤ 8A	0.594	0.6	0.606	V
MOSFET
High-side switch resistance	BOOT-PH = 3 V		32	60	mΩ
High-side switch resistance⁽¹⁾	BOOT-PH = 6 V		26	40	mΩ
Low-side Switch Resistance⁽¹⁾	VIN = 12 V		19	30	mΩ
ERROR AMPLIFIER
Error amplifier Transconductance (gm)	–2 μA < I_COMP < 2 μA, V_(COMP) = 1 V		1300		μMhos
Error amplifier dc gain	VSENSE = 0.6 V	1000	4000		V/V
Error amplifier source/sink	V_(COMP) = 1 V, 100 mV input overdrive		±110		μA
Start switching threshold			0.25		V
COMP to Iswitch gm			21		A/V
CURRENT LIMIT
High-side switch current limit threshold		10.5	14.5	17	A
Low-side switch sourcing current limit		9.5	11.5	15	A
Low-side switch sinking current limit		2	3	4	A
Hiccup wait time			512		Cycles
Hiccup time before re-start			16384		Cycles
THERMAL SHUTDOWN
Thermal shutdown		160	175		°C
Thermal shutdown hysteresis			10		°C
Thermal shutdown hiccup time			16384		Cycles
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Minimum switching frequency	Rrt = 240 kΩ (1%)	160	200	240	kHz
Switching frequency	Rrt = 100 kΩ (1%)	400	480	560	kHz
Maximum switching frequency	Rrt = 29 kΩ (1%)	1440	1600	1760	kHz
Minimum pulse width			20		ns
RT/CLK high threshold				2	V
RT/CLK low threshold		0.78			V
RT/CLK falling edge to PH rising edge delay	Measure at 500 kHz with RT resistor in series		66		ns
Switching frequency range (RT mode set point and PLL mode)		200		1600	kHz
PH (PH PIN)
Minimum on time	Measured at 90% to 90% of VIN, 25°C, I_PH = 2A		94	145	ns
Minimum off time	BOOT-PH ≥ 3 V		0		ns
BOOT (BOOT PIN)
BOOT-PH UVLO			2.1	3	V
SLOW START AND TRACKING (SS/TR PIN)
SS charge current			2.3		μA
SS/TR to VSENSE matching	V_(SS/TR) = 0.4 V		20	60	mV
POWER GOOD (PWRGD PIN)
VSENSE threshold	VSENSE falling (Fault)		92		% Vref
VSENSE rising (Good)			94		% Vref
VSENSE rising (Fault)			106		% Vref
VSENSE falling (Good)			104		% Vref
Output high leakage	VSENSE = Vref, V_(PWRGD) = 5.5 V		30	100	nA
Output low	I_(PWRGD) = 2 mA			0.3	V
Minimum VIN for valid output	V_(PWRGD) < 0.5V at 100 μA		0.6	1	V
Minimum SS/TR voltage for PWRGD				1.4	V