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  • TPS717 Low-Noise, High-Bandwidth PSRR, Low-Dropout, 150-mA Linear Regulator

    • SBVS068I February   2006  – January 2016 TPS717

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • TPS717 Low-Noise, High-Bandwidth PSRR, Low-Dropout, 150-mA Linear Regulator
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Shutdown
      3. 7.3.3 Startup and Noise Reduction Capacitor
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Minimum Load
      6. 7.3.6 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Transient Response
      2. 8.1.2 Input and Output Capacitor Requirements
      3. 8.1.3 Dropout Voltage
      4. 8.1.4 Output Noise
    2. 8.2 Typical Applications
      1. 8.2.1 Application for Fixed Voltage Versions and Adjustable Voltage Version
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Powering a PLL Integrated on an SOC
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Examples
    3. 10.3 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Module
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • DSE|6
    • MPDS287A
  • DRV|6
    • MPDS216E
  • DCK|5
    • MPDS025K
Thermal pad, mechanical data (Package|Pins)
  • DRV|6
    • QFND241B
Orderable Information
  • sbvs068i_oa
  • sbvs068i_pm
search No matches found.
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DATA SHEET

TPS717 Low-Noise, High-Bandwidth PSRR, Low-Dropout, 150-mA Linear Regulator

1 Features

  • Input Voltage: 2.5 V to 6.5 V
  • Available in Multiple Output Versions:
    • Fixed Output with Voltages from 0.9 V to 5 V
    • Adjustable Output Voltage from 0.9 V to 6.2 V
  • Ultra-High PSRR:
    • 70 dB at 1 kHz, 67 dB at 100 kHz, and
      45 dB at 1 MHz
  • Excellent Load and Line Transient Response
  • Very Low Dropout: 170 mV typical at 150 mA
  • Low Noise: 30 μVRMS typical (100 Hz to 100 kHz)
  • Small 5-pin SC-70, 2-mm × 2-mm WSON-6, and 1.5-mm × 1.5-mm WSON-6 Packages

2 Applications

  • Camera Sensor Power
  • Mobile Phone Handsets
  • PDAs and Smartphones
  • Wireless LAN, Bluetooth®

3 Description

The TPS717 family of low-dropout (LDO), low-power linear regulators offers very high power-supply rejection (PSRR) while maintaining very low 45-μA ground current in an ultra-small, five-pin SOT package. The family uses an advanced BiCMOS process and a PMOS pass device to achieve fast start-up, very low noise, excellent transient response, and excellent PSRR performance. The TPS717 is stable with a 1-μF ceramic output capacitor and uses a precision voltage reference and feedback loop to achieve a worst-case accuracy of 3% over all load, line, process, and temperature variations. The device family is fully specified from TJ = –40°C to 125°C and is offered in a small SOT (SC70-5) package, a
2-mm × 2-mm WSON-6 package with a thermal pad, and a 1.5-mm × 1.5-mm WSON-6 package, which are ideal for small form factor portable equipment (such as wireless handsets and PDAs).

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS717 SC70 (5) 2.00 mm × 1.25 mm
WSON (6) 2.00 mm × 2.00 mm
WSON (6) 1.50 mm × 1.50 mm
  1. For all available package and voltage options, see the orderable addendum at the end of the datasheet.

Typical Application Circuit for Fixed-Voltage Versions

TPS717 front_fbd_sbvs068.gif

PSRR vs Frequency

TPS717 front_tc_sbvs068.gif

4 Revision History

Changes from H Revision (January 2015) to I Revision

  • Added TI Design Go
  • Changed PMOSFET to PMOS in Description section Go
  • Added footnote to the Recommended Operating Conditions tableGo
  • Changed VFB parameter in Electrical Characteristics table Go
  • Changed units of Vn parameter in Electrical Characteristics tableGo
  • Deleted UVLO parameter minimum specification from Electrical Characteristics tableGo
  • Changed TA to TJ in x-axis of Figure 7, Figure 10, and Figure 11 Go
  • Changed second paragraph of Startup and Noise Reduction Capacitor sectionGo
  • Changed last bullet in Normal Operation section Go
  • Changed value of the TJ column in last row of Table 1 Go
  • Added last sentence to Input and Output Capacitor Requirements sectionGo
  • Changed VREF to VFB in Equation 3 Go
  • Changed definition of z in Table 4 Go

Changes from G Revision (April 2009) to H Revision

  • Changed pin descriptions throughout Pin Functions tableGo
  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Changed load regulation typical specification from 120 µV to 70 µV to better reflect device performance Go
  • Changed condition for CNR = none for Vn parameterGo
  • Changed Figure 1, Figure 2, Figure 3, and Figure 4: removed legend, added call-outs for clarityGo
  • Changed titles of Figure 15, Figure 17, and Figure 25Go
  • Corrected input and output symbols in operational amplifiers in Functional Block Diagrams Go
  • Changed Undervoltage Lockout (UVLO) section text: reworded for clarityGo
  • Deleted Reverse Current Protection section Go

Changes from F Revision (February 2009) to G Revision

  • Changed min and max specs for Output accuracy, VOUT ≥ 1.0VGo

5 Pin Configuration and Functions

DCK Package
5-Pin SC70
Top View
TPS717 po_dck_slvsbm4.gif
DRV Package
2-mm × 2-mm, 6-Pin WSON
Top View
TPS717 po_drv_slvsbm4.gif
DSE Package
1.5-mm × 1.5-mm, 6-Pin WSON
Top View
TPS717 po_dse_slvsbm4.gif
1. N/C = No connection

Pin Functions

PIN I/O DESCRIPTION
NAME DCK
(SC70)		 DRV
(WSON)		 DSE
(WSON)
EN 3 4 4 I Driving the enable pin (EN) above VEN(high) turns on the regulator. Driving this pin below VEN(low) puts the regulator into standby mode, thereby disabling the output and reducing operating current.
FB 4 2 3 I Adjustable voltage version only. The voltage at this pin is fed to the error amplifier. A resistor divider from OUT to FB sets the output voltage when in regulation.
GND 2 3 2 — Ground
IN 1 6 6 I Input to the device. A 0.1-μF to 1-μF capacitor is recommended for better performance.
N/C — 5 5 — Not connected. This pin can be tied to ground to improve thermal dissipation.
NR 4 2 3 — Fixed voltage versions only. The noise reduction capacitor filters the noise generated by the internal band gap, thus lowering output noise.
OUT 5 1 1 O This pin is the regulated output voltage. A minimum capacitance of 1 μF is required for stability from this pin to ground.

6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted), all voltages are with respect to GND(1)
MIN MAX UNIT
Voltage VIN –0.3 7 V
VFB –0.3 3.6
VNR –0.3 3.6
VEN –0.3 VIN + 0.3 V(2)
VOUT –0.3 7
Current IOUT Internally limited A
Continuous total power dissipation PDISS See Thermal Information
Operating junction temperature TJ –55 150 °C
Storage temperature Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VEN absolute maximum rating is VIN + 0.3 V or 7 V, whichever is greater.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage 2.5 6.5 V
VOUT Output voltage 0.9 5 V
IOUT Output current 0 150 mA
VEN Enable voltage 0 VIN V
COUT Output capacitor 1(1) 100 µF
TJ Junction temperature –40 125 °C
(1) When using feedback resistors that are smaller than recommended, the minimum output capacitance must be greater than 5 µF.

6.4 Thermal Information

THERMAL METRIC(1) TPS717 UNIT
DCK (SC70) DRV (WSON) DSE (WSON)
5 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 279.2 71.1 190.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 57.5 96.5 94.9 °C/W
RθJB Junction-to-board thermal resistance 74.1 40.5 149.3 °C/W
ψJT Junction-to-top characterization parameter 0.8 2.7 6.4 °C/W
ψJB Junction-to-board characterization parameter 73.1 40.9 152.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 10.7 n/a °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT = 0.5 mA, VEN = VIN, COUT = 1.0 μF, CNR = 0.01 μF, unless otherwise noted. For TPS71701, VOUT = 2.8 V. Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range(1) 2.5 6.5 V
VFB Feedback pin voltage (TPS71701) IOUT = 5 mA –2% 0.793 2% V
VOUT Output voltage range (TPS717xx) 0.9 5.0 V
(TPS71701) 0.9 6.5 – VDO
VOUT Output accuracy Nominal TJ = 25°C ±2.5 mV
Output accuracy
(VOUT < 1.0 V)		 Over VIN, IOUT, temperature(3) VOUT + 0.5 V ≤ VIN ≤ 6.5 V
0 mA ≤ IOUT ≤ 150 mA		 –30 30
Output accuracy
(VOUT ≥ 1.0 V)		 Over VIN, IOUT, temperature(3) VOUT + 0.5 V ≤ VIN ≤ 6.5 V
0 mA ≤ IOUT ≤ 150 mA		 –3.0% 3.0%
ΔVOUT(ΔVIN) Line regulation(1) VOUT(nom) + 0.5 V ≤ VIN ≤ 6.5 V,
IOUT = 5 mA		 125 µV/V
ΔVOUT(ΔIOUT) Load regulation 0 mA ≤ IOUT ≤ 150 mA 70 µV/mA
VDO Dropout voltage(2)
(VIN = VOUT(nom) – 0.1 V)		 IOUT = 150 mA 170 300 mV
ILIM (fixed) Output current limit (fixed output) VOUT = 0.9 × VOUT(nom) 200 325 575 mA
ILIM (adjustable) Output current limit (TPS71701) VOUT = 0.9 × VOUT(nom) 200 325 575 mA
IGND Ground pin current IOUT = 0.1 mA 45 80 μA
IOUT = 150 mA 100
ISHDN Shutdown current (IGND) VEN ≤ 0.4 V,
TJ = –40°C to 85°C		 2.5 V ≤ VIN < 4.5 V 0.20 1.5 μA
4.5 V ≤ VIN ≤ 6.5 V 0.90
IFB Feedback pin current (TPS71701) 0.02 1.0 μA
PSRR Power-supply rejection ratio VIN = 3.8 V,
VOUT = 2.8 V,
IOUT = 150 mA		 f = 100 Hz 70 dB
f = 1 kHz 70
f = 10 kHz 67
f = 100 kHz 67
f = 1 MHz 45
Vn Output noise voltage BW = 100 Hz to 100 kHz,
VIN = 3.8 V,
VOUT = 2.8 V,
IOUT = 10 mA		 CNR = none 95 × VOUT μVRMS/V
CNR = 0.001 μF 25 × VOUT
CNR = 0.01 μF 12.5 × VOUT
CNR = 0.1 μF 11.5 × VOUT
tSTR Startup time VOUT = 90% VOUT(nom),
RL = 19 Ω,
COUT = 1 μF		 0.9 V ≤ VOUT ≤ 1.6V, CNR = 0.001 μF 0.700 ms
1.6 V < VOUT < VMAX, CNR = 0.01 μF 0.160
VEN(high) Enable high (enabled) VIN ≤ 5.5 V 1.2 6.5(4) V
5.5 V < VIN ≤ 6.5 V 1.25 6.5
VEN(low) Enable low (shutdown) 0 0.4 V
IEN(high) Enable pin current, enabled EN = 6.5 V 0.02 1.0 μA
UVLO Undervoltage lockout VIN rising 2.45 2.49 V
Hysteresis VIN falling 150 mV
Tsd Thermal shutdown temperature Shutdown, temperature increasing 160 °C
Reset, temperature decreasing 140
TJ Operating junction temperature –40 125 °C
(1) Minimum VIN = VOUT + VDO or 2.5 V, whichever is greater.
(2) VDO is not measured for devices with VOUT(nom) < 2.6 V because the minimum VIN is 2.5 V.
(3) Does not include external resistor tolerances.
(4) Maximum VEN(high) = VIN + 0.3 or 6.5 V, whichever is smaller.

6.6 Typical Characteristics

Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT = 0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701,) VOUT = 2.8 V. Typical values are at TA = 25°C.
TPS717 tc_load_bvs068.gif
Figure 1. Load Regulation
TPS717 tc_line_bvs068.gif
Figure 3. Line Regulation (IOUT = 5 mA)
TPS717 tc_vout_temp_bvs068.gif
Figure 5. Output Voltage vs Temperature
TPS717 tc_vdo_temp_bvs068.gif
Figure 7. Dropout Voltage vs Temperature
TPS717 tc_ignd_io_bvs068.gif
Figure 9. Ground Pin Current vs Output Current
TPS717 tc_ignd_temp_dis_bvs068.gif
Figure 11. Ground Pin Current vs Temperature (Disabled)
TPS717 tc_psrr_fqcy01_bvs068.gif
Figure 13. Power-Supply Ripple Rejection vs Frequency (VIN – VOUT = 1 V)
TPS717 tc_psrr_fqcy03_bvs068.gif
Figure 15. Power-Supply Ripple Rejection vs Frequency in Dropout Conditions (VIN – VOUT = 0.25 V)
TPS717 tc_psrr_fqcy05_bvs068.gif
Figure 17. Power-Supply Ripple Rejection vs Frequency in Dropout Conditions (VIN – VOUT = 0.25 V)
TPS717 tc_psrr_iout01_bvs068.gif
Figure 19. Power-Supply Ripple Rejection vs (VIN – VOUT)
TPS717 tc_psrr_iout03_bvs068.gif
Figure 21. Power-Supply Ripple Rejection vs (VIN – VOUT)
TPS717 tc_noise_cout_bvs068.gif
Figure 23. Output Spectral Noise Density vs
Output Capacitance
TPS717 tc_noisetotal_cnr_bvs068.gif
Figure 25. Total Output Noise vs Noise Reduction Capacitor
TPS717 tc_line_tr_slvsbm4.gif
Figure 27. Line Transient Response
TPS717 tc_turn-on_bvs068.gif
Figure 29. Turn-On Response
TPS717 tc_light_load_bvs068.gif
Figure 2. Load Regulation Under Light Loads
TPS717 tc_line02_bvs068.gif
Figure 4. Line Regulation (IOUT = 150 mA)
TPS717 tc_vdo_io_bvs068.gif
Figure 6. Dropout Voltage vs Output Current
TPS717 tc_ignd_vin_lvsbm4.gif
Figure 8. Ground Pin Current vs Input Voltage
TPS717 tc_ignd_temp_en_bvs068.gif
Figure 10. Ground Pin Current vs Temperature (Enabled)
TPS717 tc_iclamp_vin_lvsbm4.gif
Figure 12. Current Limit vs Input Voltage
TPS717 tc_psrr_fqcy02_bvs068.gif
Figure 14. Power-Supply Ripple Rejection vs Frequency (VIN – VOUT = 0.5 V)
TPS717 tc_psrr_fqcy04_bvs068.gif
Figure 16. Power-Supply Ripple Rejection vs Frequency (VIN – VOUT = 1 V)
TPS717 tc_psrr_fqcy06_bvs068.gif
Figure 18. Power-Supply Ripple Rejection vs Frequency (VIN – VOUT = 1 V)
TPS717 tc_psrr_iout02_bvs068.gif
Figure 20. Power-Supply Ripple Rejection vs (VIN – VOUT)
TPS717 tc_noise_iout_bvs068.gif
Figure 22. Output Spectral Noise Density vs
Output Current
TPS717 tc_noise_cnr_bvs068.gif
Figure 24. Output Spectral Noise Density vs
Noise Reduction
TPS717 tc_noisetotal_cout_bvs068.gif
Figure 26. Total Output Noise vs Output Capacitance
TPS717 tc_load_tr_slvsbm4.gif
Figure 28. Load Transient Response
TPS717 tc_pupd_bvs068.gif
Figure 30. Power-Up and Power-Down

7 Detailed Description

7.1 Overview

The TPS717 family of low-dropout (LDO) regulators combines the high performance required by many RF and precision analog applications with ultra-low current consumption. High PSRR is provided by a high-gain, high-bandwidth error loop with good supply rejection with very low headroom (VIN – VOUT). Fixed voltage versions provide a noise reduction pin to bypass noise generated by the band-gap reference and to improve PSRR. A quick-start circuit fast-charges this capacitor at startup. The combination of high performance and low ground current also make the TPS717 family of devices an excellent choice for battery-powered applications. All versions have thermal and overcurrent protection.

7.2 Functional Block Diagrams

TPS717 fbd1_fixed_lvsbm4.gif Figure 31. Fixed Voltage Versions
TPS717 fbd2_adjust_lvsbm4.gif Figure 32. Adjustable Voltage Version

7.3 Feature Description

7.3.1 Internal Current Limit

The TPS717 internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, do not operate the device in a current-limit state for extended periods of time.

The PMOS pass element in the TPS717 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting may be appropriate.

7.3.2 Shutdown

The enable pin (EN) is active high and compatible with standard and low voltage, TTL-CMOS levels. When shutdown capability is not required, EN can be connected to IN.

7.3.3 Startup and Noise Reduction Capacitor

Fixed voltage versions of the TPS717 use a quick-start circuit to fast-charge the noise reduction capacitor, CNR, if present (see Figure 31). This circuit allows the combination of very low output noise and fast start-up times. The NR pin is high impedance, so a low-leakage CNR capacitor must be used; most ceramic capacitors are appropriate in this configuration.

Note that for fastest startup, apply VIN first, then drive the enable pin high. If EN is tied to IN, startup is somewhat slower. The quick-start switch is closed for approximately 135 μs. To ensure that CNR is fully charged during the quick-start time, use a 0.01-μF or smaller capacitor.

For output voltages below 1.6 V, a voltage divider on the band-gap reference voltage is employed to optimize output regulation performance for lower output voltages. This configuration results in an additional resistor in the quick-start path and combined with the noise reduction capacitor (CNR) results in slower start-up times for output voltages below 1.6 V.

Equation 1 approximates the start-up time as a function of CNR for output voltages below 1.6 V:

Equation 1. TPS717 q_startup_bvs068.gif

7.3.4 Undervoltage Lockout (UVLO)

The TPS717 uses an undervoltage lockout circuit to keep the output shut off until the internal circuitry is operating properly. The UVLO circuit has a limited glitch immunity so undershoot transients are typically ignored on the input if these transients are less than 5 μs in duration. When the input is lower than 1.4 V, the UVLO circuit may not have enough headroom to keep the output fully off.

7.3.5 Minimum Load

The TPS717 is stable with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at very light output loads. The TPS717 employs an innovative low-current mode circuit to increase loop gain under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current.

7.3.6 Thermal Protection

Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage because of overheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, limit junction temperature to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, trigger thermal protection at least 35°C above the maximum expected ambient condition of a particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TPS717 is designed to protect against overload conditions. This circuitry is not intended to replace proper heatsinking. Continuously running the TPS717 into thermal shutdown degrades device reliability.

7.4 Device Functional Modes

7.4.1 Normal Operation

The device regulates to the nominal output voltage under the following conditions:

  • The input voltage has previously exceeded the UVLO rising voltage and has not decreased below the UVLO falling threshold
  • The input voltage is greater than the nominal output voltage added to the dropout voltage
  • The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased below the enable falling threshold
  • The output current is less than the current limit
  • The device junction temperature is less than or equal to the maximum specified operating junction temperature

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this condition, the output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device is in a triode state and no longer controls the current through the LDO. Line or load transients in dropout can result in large output voltage deviations.

7.4.3 Disabled

The device is disabled under the following conditions:

  • The input voltage is less than the UVLO falling voltage, or has not yet exceeded the UVLO rising threshold.
  • The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising threshold.
  • The device junction temperature is greater than the thermal shutdown temperature.

Table 1 shows the conditions that lead to the different modes of operation.

Table 1. Device Functional Mode Comparison

OPERATING MODE PARAMETER
VIN VEN IOUT TJ
Normal mode VIN > VOUT(nom) + VDO and VIN > UVLO VEN > VEN(high) I OUT < ILIM T J < 125°C
Dropout mode UVLO < VIN < VOUT(nom) + VDO VEN > VEN(high) — TJ < 125°C
Disabled mode
(any true condition disables the device)		 VIN < UVLO – Vhys VEN < VEN(low) — TJ > 160°C

 
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