The TPS717 family of low-dropout (LDO), low-power linear regulators offers very high power-supply rejection (PSRR) while maintaining very low 45-μA ground current in an ultra-small, five-pin SOT package. The family uses an advanced BiCMOS process and a PMOS pass device to achieve fast start-up, very low noise, excellent transient response, and excellent PSRR performance. The TPS717 is stable with a 1-μF ceramic output capacitor and uses a precision voltage reference and feedback loop to achieve a worst-case accuracy of 3% over all load, line, process, and temperature variations. The device family is fully specified from TJ = –40°C to 125°C and is offered in a small SOT (SC70-5) package, a
2-mm × 2-mm WSON-6 package with a thermal pad, and a 1.5-mm × 1.5-mm WSON-6 package, which are ideal for small form factor portable equipment (such as wireless handsets and PDAs).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS717 | SC70 (5) | 2.00 mm × 1.25 mm |
WSON (6) | 2.00 mm × 2.00 mm | |
WSON (6) | 1.50 mm × 1.50 mm |
Changes from H Revision (January 2015) to I Revision
Changes from G Revision (April 2009) to H Revision
Changes from F Revision (February 2009) to G Revision
PIN | I/O | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | DCK (SC70) |
DRV (WSON) |
DSE (WSON) |
||
EN | 3 | 4 | 4 | I | Driving the enable pin (EN) above VEN(high) turns on the regulator. Driving this pin below VEN(low) puts the regulator into standby mode, thereby disabling the output and reducing operating current. |
FB | 4 | 2 | 3 | I | Adjustable voltage version only. The voltage at this pin is fed to the error amplifier. A resistor divider from OUT to FB sets the output voltage when in regulation. |
GND | 2 | 3 | 2 | — | Ground |
IN | 1 | 6 | 6 | I | Input to the device. A 0.1-μF to 1-μF capacitor is recommended for better performance. |
N/C | — | 5 | 5 | — | Not connected. This pin can be tied to ground to improve thermal dissipation. |
NR | 4 | 2 | 3 | — | Fixed voltage versions only. The noise reduction capacitor filters the noise generated by the internal band gap, thus lowering output noise. |
OUT | 5 | 1 | 1 | O | This pin is the regulated output voltage. A minimum capacitance of 1 μF is required for stability from this pin to ground. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | VIN | –0.3 | 7 | V |
VFB | –0.3 | 3.6 | ||
VNR | –0.3 | 3.6 | ||
VEN | –0.3 | VIN + 0.3 V(2) | ||
VOUT | –0.3 | 7 | ||
Current | IOUT | Internally limited | A | |
Continuous total power dissipation | PDISS | See Thermal Information | ||
Operating junction temperature | TJ | –55 | 150 | °C |
Storage temperature | Tstg | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | Input voltage | 2.5 | 6.5 | V | |
VOUT | Output voltage | 0.9 | 5 | V | |
IOUT | Output current | 0 | 150 | mA | |
VEN | Enable voltage | 0 | VIN | V | |
COUT | Output capacitor | 1(1) | 100 | µF | |
TJ | Junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS717 | UNIT | |||
---|---|---|---|---|---|
DCK (SC70) | DRV (WSON) | DSE (WSON) | |||
5 PINS | 6 PINS | 6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 279.2 | 71.1 | 190.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 57.5 | 96.5 | 94.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 74.1 | 40.5 | 149.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.8 | 2.7 | 6.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 73.1 | 40.9 | 152.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | 10.7 | n/a | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
VIN | Input voltage range(1) | 2.5 | 6.5 | V | ||||
VFB | Feedback pin voltage (TPS71701) | IOUT = 5 mA | –2% | 0.793 | 2% | V | ||
VOUT | Output voltage range | (TPS717xx) | 0.9 | 5.0 | V | |||
(TPS71701) | 0.9 | 6.5 – VDO | ||||||
VOUT | Output accuracy | Nominal | TJ = 25°C | ±2.5 | mV | |||
Output accuracy (VOUT < 1.0 V) |
Over VIN, IOUT, temperature(3) | VOUT + 0.5 V ≤ VIN ≤ 6.5 V 0 mA ≤ IOUT ≤ 150 mA |
–30 | 30 | ||||
Output accuracy
(VOUT ≥ 1.0 V) |
Over VIN, IOUT, temperature(3) | VOUT + 0.5 V ≤ VIN ≤ 6.5 V 0 mA ≤ IOUT ≤ 150 mA |
–3.0% | 3.0% | ||||
ΔVOUT(ΔVIN) | Line regulation(1) | VOUT(nom) + 0.5 V ≤ VIN ≤ 6.5 V, IOUT = 5 mA |
125 | µV/V | ||||
ΔVOUT(ΔIOUT) | Load regulation | 0 mA ≤ IOUT ≤ 150 mA | 70 | µV/mA | ||||
VDO | Dropout voltage(2)
(VIN = VOUT(nom) – 0.1 V) |
IOUT = 150 mA | 170 | 300 | mV | |||
ILIM (fixed) | Output current limit (fixed output) | VOUT = 0.9 × VOUT(nom) | 200 | 325 | 575 | mA | ||
ILIM (adjustable) | Output current limit (TPS71701) | VOUT = 0.9 × VOUT(nom) | 200 | 325 | 575 | mA | ||
IGND | Ground pin current | IOUT = 0.1 mA | 45 | 80 | μA | |||
IOUT = 150 mA | 100 | |||||||
ISHDN | Shutdown current (IGND) | VEN ≤ 0.4 V, TJ = –40°C to 85°C |
2.5 V ≤ VIN < 4.5 V | 0.20 | 1.5 | μA | ||
4.5 V ≤ VIN ≤ 6.5 V | 0.90 | |||||||
IFB | Feedback pin current (TPS71701) | 0.02 | 1.0 | μA | ||||
PSRR | Power-supply rejection ratio | VIN = 3.8 V, VOUT = 2.8 V, IOUT = 150 mA |
f = 100 Hz | 70 | dB | |||
f = 1 kHz | 70 | |||||||
f = 10 kHz | 67 | |||||||
f = 100 kHz | 67 | |||||||
f = 1 MHz | 45 | |||||||
Vn | Output noise voltage | BW = 100 Hz to 100 kHz, VIN = 3.8 V, VOUT = 2.8 V, IOUT = 10 mA |
CNR = none | 95 × VOUT | μVRMS/V | |||
CNR = 0.001 μF | 25 × VOUT | |||||||
CNR = 0.01 μF | 12.5 × VOUT | |||||||
CNR = 0.1 μF | 11.5 × VOUT | |||||||
tSTR | Startup time | VOUT = 90% VOUT(nom), RL = 19 Ω, COUT = 1 μF |
0.9 V ≤ VOUT ≤ 1.6V, CNR = 0.001 μF | 0.700 | ms | |||
1.6 V < VOUT < VMAX, CNR = 0.01 μF | 0.160 | |||||||
VEN(high) | Enable high (enabled) | VIN ≤ 5.5 V | 1.2 | 6.5(4) | V | |||
5.5 V < VIN ≤ 6.5 V | 1.25 | 6.5 | ||||||
VEN(low) | Enable low (shutdown) | 0 | 0.4 | V | ||||
IEN(high) | Enable pin current, enabled | EN = 6.5 V | 0.02 | 1.0 | μA | |||
UVLO | Undervoltage lockout | VIN rising | 2.45 | 2.49 | V | |||
Hysteresis | VIN falling | 150 | mV | |||||
Tsd | Thermal shutdown temperature | Shutdown, temperature increasing | 160 | °C | ||||
Reset, temperature decreasing | 140 | |||||||
TJ | Operating junction temperature | –40 | 125 | °C |
The TPS717 family of low-dropout (LDO) regulators combines the high performance required by many RF and precision analog applications with ultra-low current consumption. High PSRR is provided by a high-gain, high-bandwidth error loop with good supply rejection with very low headroom (VIN – VOUT). Fixed voltage versions provide a noise reduction pin to bypass noise generated by the band-gap reference and to improve PSRR. A quick-start circuit fast-charges this capacitor at startup. The combination of high performance and low ground current also make the TPS717 family of devices an excellent choice for battery-powered applications. All versions have thermal and overcurrent protection.
The TPS717 internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, do not operate the device in a current-limit state for extended periods of time.
The PMOS pass element in the TPS717 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting may be appropriate.
The enable pin (EN) is active high and compatible with standard and low voltage, TTL-CMOS levels. When shutdown capability is not required, EN can be connected to IN.
Fixed voltage versions of the TPS717 use a quick-start circuit to fast-charge the noise reduction capacitor, CNR, if present (see Figure 31). This circuit allows the combination of very low output noise and fast start-up times. The NR pin is high impedance, so a low-leakage CNR capacitor must be used; most ceramic capacitors are appropriate in this configuration.
Note that for fastest startup, apply VIN first, then drive the enable pin high. If EN is tied to IN, startup is somewhat slower. The quick-start switch is closed for approximately 135 μs. To ensure that CNR is fully charged during the quick-start time, use a 0.01-μF or smaller capacitor.
For output voltages below 1.6 V, a voltage divider on the band-gap reference voltage is employed to optimize output regulation performance for lower output voltages. This configuration results in an additional resistor in the quick-start path and combined with the noise reduction capacitor (CNR) results in slower start-up times for output voltages below 1.6 V.
Equation 1 approximates the start-up time as a function of CNR for output voltages below 1.6 V:
The TPS717 uses an undervoltage lockout circuit to keep the output shut off until the internal circuitry is operating properly. The UVLO circuit has a limited glitch immunity so undershoot transients are typically ignored on the input if these transients are less than 5 μs in duration. When the input is lower than 1.4 V, the UVLO circuit may not have enough headroom to keep the output fully off.
The TPS717 is stable with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at very light output loads. The TPS717 employs an innovative low-current mode circuit to increase loop gain under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current.
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage because of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, limit junction temperature to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, trigger thermal protection at least 35°C above the maximum expected ambient condition of a particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS717 is designed to protect against overload conditions. This circuitry is not intended to replace proper heatsinking. Continuously running the TPS717 into thermal shutdown degrades device reliability.
The device regulates to the nominal output voltage under the following conditions:
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this condition, the output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device is in a triode state and no longer controls the current through the LDO. Line or load transients in dropout can result in large output voltage deviations.
The device is disabled under the following conditions:
Table 1 shows the conditions that lead to the different modes of operation.