TPS7A47-Q1 35-V, 1-A, 4.2-µVRMS, RF LDO Voltage Regulator
- SBVS118 August 2017 TPS7A47-Q1
  
  PRODUCTION DATA.

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DATA SHEET

TPS7A47-Q1 35-V, 1-A, 4.2-µVRMS, RF LDO Voltage Regulator

1 Features

Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
- Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
- Device HBM ESD Classification Level 2
- Device CDM ESD Classification Level C4A
Input Voltage: 3 V to 35 V
Operating Junction Temperature: –40°C to +145°C
Output Voltage Noise:
4.2 µV_RMS (10 Hz–100 kHz)
Power-Supply Rejection Ratio:
- 82 dB (100 Hz)
- ≥ 55 dB (10 Hz–10 MHz)
Two Output Voltage Modes:
- ANY-OUT™ Version (User-Programmable Output via PCB Layout):
  - Output Voltage: 1.4 V to 20.5 V
- Adjustable Operation:
  - Output Voltage: 1.4 V to 34 V
Output Current: 1 A
Thermal resistance: θ_JA = 31.1°C/W
Dropout Voltage: 307 mV at 1 A
CMOS Logic Level-Compatible Enable Pin
Built-In Fixed Current Limit and
Thermal Shutdown

2 Applications

Voltage-Controlled Oscillators (VCO)
Rx, Tx, and PA Circuitry
Automotive Infotainment and Cluster
Supply Rails for Operational Amplifiers,
DACs, ADCs, and Other High-Precision Analog Circuitry

3 Description

The TPS7A47-Q1 device is a positive voltage (35 V), ultra-low-noise (4.2 µV_RMS) low-dropout linear regulator (LDO) capable of sourcing a 1-A load.

The TPS7A47-Q1 output voltage can be configured with a user-programmable printed circuit board (PCB) layout (up to 20.5 V), or adjustable (up to 34 V) with external feedback resistors.

The TPS7A47-Q1 is designed with bipolar technology primarily for high-accuracy, high-precision instrumentation applications where clean voltage rails are critical to maximize system performance. This feature makes the device ideal for powering operational amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other high-performance analog circuitry.

In addition, the TPS7A47-Q1 is ideal for post dc-dc converter regulation. By filtering out the output voltage ripple inherent to dc-dc switching conversions, maximum system performance is ensured in sensitive instrumentation, audio, and RF applications.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS7A47-Q1	VQFN (20)	5.00 mm × 5.00 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

4 Revision History

DATE	REVISION	NOTES
August 2017	*	Initial release.

5 Pin Configuration and Functions

RGW Package

5-mm × 5-mm, 20-Pin VQFN

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
0P1V	12	I	When connected to GND, this pin adds 0.1 V to the nominal output voltage of the regulator. Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
0P2V	11	I	When connected to GND, this pin adds 0.2 V to the nominal output voltage of the regulator. Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
0P4V	10	I	When connected to GND, this pin adds 0.4 V to the nominal output voltage of the regulator. Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
0P8V	9	I	When connected to GND, this pin adds 0.8 V to the nominal output voltage of the regulator. Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
1P6V	8	I	When connected to GND, this pin adds 1.6 V to the nominal output voltage of the regulator. Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
3P2V	6	I	When connected to GND, this pin adds 3.2 V to the nominal output voltage of the regulator. Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
6P4V1	5	I	When connected to GND, this pin adds 6.4 V to the nominal output voltage of the regulator. Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
6P4V2	4	I	When connected to GND, this pin adds 6.4 V to the nominal output voltage of the regulator. Do not connect any voltage other than GND to this pin. If not used, leave this pin floating.
EN	13	I	Enable pin. The device is enabled when the voltage on this pin exceeds the maximum enable voltage, V_EN(HI). If enable is not required, tie EN to IN.
GND	7	—	Ground
IN	15, 16	I	Input supply. A capacitor greater than or equal to 1 µF must be tied from this pin to ground to assure stability. A 10-µF capacitor is recommended to be connected from IN to GND (as close to the device as possible) to reduce circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or high source impedances are encountered.
NC	2, 17-19	—	This pin can be left open or tied to any voltage between GND and IN.
NR	14	—	Noise-reduction pin. When a capacitor is connected from this pin to GND, RMS noise can be reduced to very low levels. A capacitor greater than or equal to 10 nF must be tied from this pin to ground to assure stability. A 1-µF capacitor is recommended to be connected from NR to GND (as close to the device as possible) to maximize ac performance and minimize noise.
OUT	1, 20	O	Regulator output. A capacitor greater than or equal to 10 µF must be tied from this pin to ground to assure stability. A 47-µF ceramic output capacitor is highly recommended to be connected from OUT to GND (as close to the device as possible) to maximize ac performance.
SENSE/FB	3	I	Control-loop error amplifier input. This pin is the SENSE pin if the device output voltage is programmed using ANY-OUT (no external feedback resistors). This pin must be connected to OUT. Connect this pin to the point of load to maximize accuracy. This pin is the FB pin if the device output voltage is set using external resistors. See the Adjustable Operation Adjustable Operation section for more details.
PowerPAD	Pad	—	Connect the PowerPAD to a large-area ground plane. The PowerPAD™ is internally connected to GND.

6 Specifications

6.1 Absolute Maximum Ratings

over junction temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage⁽²⁾	IN pin (V_I) to GND pin	–0.4	36	V
	EN pin to GND pin	–0.4	36
	EN pin to IN pin	–36	0.4
	OUT pin to GND pin	–0.4	V_I + 0.3
	NR pin to GND pin	–0.4	V_I + 0.3⁽³⁾
	SENSE/FB pin to GND pin	–0.4	V_I + 0.3
	0P1V pin to GND pin	–0.4	2.5
	0P2V pin to GND pin	–0.4	2.5
	0P4V pin to GND pin	–0.4	2.5
	0P8V pin to GND pin	–0.4	2.5
	1P6V pin to GND pin	–0.4	2.5
	3P2V pin to GND pin	–0.4	2.5
	6P4V1 pin to GND pin	–0.4	2.5
	6P4V2 pin to GND pin	–0.4	2.5
Current	Peak output	Internally limited
Temperature	Operating virtual junction, T_J	–40	145	°C
Temperature	Storage, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the network ground terminal.

(3) The absolute maximum rating is V_I + 0.3 V or 22 V, whichever is smaller.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±500	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over junction temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_I	Input voltage	3.0	35.0	V
C_OUT	Output capacitor	10		µF
V_+EN(HI)	Enable high-level voltage	2.0	V_I	V
V_+EN(LO)	Enable low-level voltage	0	0.4	V
I_O	Output current	0	1.0	A
T_J	Operating junction temperature	–40	145	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS7A47-Q1	UNIT
		RGW (VQFN)
		20 PINS
R_θJA	Junction-to-ambient thermal resistance	31.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	21.1	°C/W
R_θJB	Junction-to-board thermal resistance	10.2	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	10.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at –40°C ≤ T_J ≤ 145°C; V_I = V_O(nom) + 1.0 V or V_I = 3.0 V (whichever is greater); V_EN = V_I; I_O = 0 mA; C_IN = 10 µF; C_OUT = 10 µF; C_NR = 10 nF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins open (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_UVLO	Undervoltage lockout threshold	V_I rising		2.67		V
V_UVLO	Undervoltage lockout threshold	V_I falling		2.5		V
V_(REF)	Reference voltage	V_(REF) = V_(FB),		1.4		V
V_UVLO(HYS)	Under-voltage lockout hysteresis			177		mV
V_NR	Noise reduction pin voltage	Using ANY-OUT option		V_OUT		V
V_NR	Noise reduction pin voltage	In adjustable mode only		1.4		V
V_O	Output voltage range	C_OUT = 20 µF, using ANY-OUT option	1.4		20.5	V
V_O	Output voltage range	C_OUT = 20 µF, using adjustable option	1.4		34	V
	Nominal V_O accuracy	T_J = 25°C, C_OUT = 20 µF	–1.0		1.0	%V_O
	Overall V_O accuracy	V_O(nom) + 1.0 V ≤ V_I ≤ 35 V, 0 mA ≤ I_O ≤ 1 A, C_OUT = 20 µF	–2.5		2.5	%V_O
ΔV_O(ΔVI)	Line regulation	V_O(nom) + 1.0 V ≤ V_I ≤ 35 V		0.092		%V_O
ΔV_O(ΔIO)	Load regulation	0 mA ≤ I_O ≤ 1 A		0.3		%V_O
V_(DO)	Dropout voltage	V_I = 95% V_O(nom), I_O = 0.5 A		216		mV
V_(DO)	Dropout voltage	V_I = 95% V_O(nom), I_O = 1 A		307	450	mV
I_(CL)	Current limit	V_O = 90% V_O(nom)	1	1.26		A
I_(GND)	Ground pin current	I_O = 0 mA		0.58	1.0	mA
I_(GND)	Ground pin current	I_O = 1 A		6.1		mA
I_(EN)	Enable pin current	V_EN = V_I		0.78	2	µA
I_(EN)	Enable pin current	V_I = V_EN = 35 V		0.81	2	µA
I_(SHDN)	Shutdown supply current	V_EN = 0.4 V		2.55	8	µA
I_(SHDN)	Shutdown supply current	V_EN = 0.4 V, V_I = 35 V		3.04	60	µA
I_(FB)	Feedback pin current			350		nA
PSRR	Power-supply rejection ratio	V_I = 16 V, V_O(nom) = 15 V, C_OUT = 50 µF, I_O = 500 mA, C_NR = 1 µF, f = 1 kHz		78		dB
V_n	Output noise voltage	V_I = 3 V, V_O(nom) = 1.4 V, C_OUT = 50 µF, C_NR = 1 µF, BW = 10 Hz to 100 kHz		4.17		µV_RMS
V_n	Output noise voltage	V_IN = 6 V, V_O(nom) = 5 V, C_OUT = 50 µF, C_NR = 1 µF, BW = 10 Hz to 100 kHz		4.67		µV_RMS
T_sd	Thermal shutdown temperature	Shutdown, temperature increasing		170		°C
T_sd	Thermal shutdown temperature	Reset, temperature decreasing		150		°C

6.6 Typical Characteristics

at T_J = 25°C; V_I = V_O(nom) + 1.0 V or V_I = 3.0 V (whichever is greater); V_EN = V_I; I_O = 0 mA; C_IN = 10 µF; C_OUT = 10 µF; C_NR = 1 µF; SENSE/FB tied to OUT; and 0P1V, 0P2V, 0P4V, 0P8V, 1P6V, 3P2V, 6P4V1, 6P4V2 pins open (unless otherwise noted)

I_OUT = 500 mA, C_OUT = 50 µF, C_NR = 1 µF,
BW_RMSNOISE (10 Hz, 100 kHz)

Figure 1. Noise vs Output Voltage

Figure 3. Load Regulation

Figure 5. Enable Voltage Threshold vs Temperature

Figure 7. Ground Current vs Output Current

Figure 9. Shutdown Current vs Input Voltage

I_OUT = 1 A, C_OUT = 50 µF, V_IN = 3 V, V_OUT = 1.4 V

Figure 11. Power-Supply Rejection Ratio vs
Frequency and C_NR

C_NR = 1 µF, C_OUT = 50 µF, V_IN = 3 V, V_OUT = 1.4 V

Figure 13. Power-Supply Rejection Ratio vs
Frequency and I_O

V_OUT = 3.3 V, C_NR = 1 µF, C_OUT = 50 µF, I_OUT = 500 mA

Figure 15. Power-Supply Rejection Ratio vs
Frequency and V_DO

C_NR = 1 µF, C_OUT = 50 µF, I_OUT = 500 mA

Figure 17. Power-Supply Rejection Ratio vs
Frequency and V_OUT

V_IN = 5 V, V_OUT = 3.3 V, I_OUT = 10 mA to 845 mA

Figure 19. Load Transient

Startup time = 65 ms, V_IN = 6 V, V_OUT = 5V, I_OUT = 500 mA,
C_IN = 10 µF, C_OUT = 50 µF

Figure 21. Startup

Figure 2. Line Regulation

Figure 4. Input Voltage Threshold vs Temperature

I_OUT = 0 µA

Figure 6. Quiescent Current vs Input Voltage

Figure 8. Enable Current vs Input Voltage

V_OUT = 90% V_OUT(NOM)

Figure 10. Current Limit vs Input Voltage

I_OUT = 0.5 A, C_OUT = 50 µF, V_IN = 3 V, V_OUT = 1.4 V

Figure 12. Power-Supply Rejection Ratio vs
Frequency and C_NR

V_OUT = 3.3 V, C_NR = 1 µF, C_OUT = 50 µF, I_OUT = 50 mA

Figure 14. Power-Supply Rejection Ratio vs
Frequency and V_DO

V_OUT = 3.3 V, C_NR = 1 µF, C_OUT = 50 µF, I_OUT = 1 A

Figure 16. Power-Supply Rejection Ratio vs
Frequency and V_DO

C_NR = 1 µF, C_OUT = 50 µF, I_OUT = 1000 mA

Figure 18. Power-Supply Rejection Ratio vs
Frequency and V_OUT

V_IN = 5 V to 15 V, V_OUT = 3.3 V, I_OUT = 845 mA

Figure 20. Line Transient

V_OUT = 4.7 V, C_OUT = 10 µF, C_NR = 1 µF, BW_RMSNOISE (10 Hz, 100 kHz)

Figure 22. Noise vs Output Current

7 Detailed Description

7.1 Overview

The TPS7A47-Q1 is a positive voltage (35 V), ultralow-noise (4.2 µV_RMS) LDO capable of sourcing a 1-A load. The TPS7A47-Q1 is designed with bipolar technology primarily for high-accuracy, high-precision instrumentation applications where clean voltage rails are critical to maximize system performance. This feature makes the device ideal for powering operational amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other high-performance analog circuitry.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Internal Current Limit (I_CL)

The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The LDO is not designed to operate at a steady-state current limit. During a current-limit event, the LDO sources constant current. Therefore, the output voltage falls when load impedance decreases. Also, when a current limit occurs while the resulting output voltage is low, excessive power is dissipated across the LDO, which results in a thermal shutdown of the output.

7.3.2 Enable (EN) And Undervoltage Lockout (UVLO)

The TPS7A47-Q1 only turns on when both EN and UVLO are above the respective voltage thresholds. The UVLO circuit monitors input voltage (V_I) to prevent device turn-on before V_I rises above the lockout voltage. The UVLO circuit also causes a shutdown when V_I falls below lockout. The EN signal allows independent logic-level turn-on and shutdown of the LDO when the input voltage is present. EN can be connected directly to V_I if independent turn-on is not needed.

7.3.3 Soft-Start And Inrush Current

Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO have achieved the threshold voltage. The noise-reduction capacitor serves a dual purpose of both governing output noise reduction and programming the soft-start ramp during turn-on.

Inrush current is defined as the current through the LDO from IN to OUT during the time of the turn-on ramp up. Inrush current then consists primarily of the sum of load and charge current to the output capacitor. Use Equation 1 to estimate in-rush current:

Equation 1. TPS7A47-Q1 q_iout-t_bvs204.gif

where

V_OUT(t) is the instantaneous output voltage of the turn-on ramp
dV_OUT(t) / dt is the slope of the V_O ramp
R_LOAD is the resistive load impedance

7.4 Device Functional Modes

The TPS7A47-Q1 has the following functional modes:

Enabled: when EN goes above V_+EN(HI), the device is enabled.
Disabled: when EN goes below V_+EN(LO), the device is disabled. During this time, OUT is high impedance, and the current into IN does not exceed I_(SHDN).

7.5 Programming

7.5.1 ANY-OUT Programmable Output Voltage

For ANY-OUT operation, do not use external resistors to set the output voltage, but use device pins 4, 5, 6, 8, 9, 10, 11, and 12 to program the regulated output voltage. Each pin is either connected to ground (active) or is left open (floating). The ANY-OUT programming is set by Equation 2 as the sum of the internal reference voltage (V_(REF) = 1.4 V) plus the accumulated sum of the respective voltages assigned to each active pin; that is, 100 mV (pin 12), 200 mV (pin 11), 400 mV (pin 10), 800 mV (pin 9), 1.6 V (pin 8), 3.2 V (pin 6), 6.4 V (pin 5), or 6.4 V (pin 4). Table 1 summarizes these voltage values associated with each active pin setting for reference. By leaving all program pins open, or floating, the output is thereby programmed to the minimum possible output voltage equal to V_(REF).

Equation 2. TPS7A47-Q1 q_vout_anyout_bvs204.gif

Table 1. ANY-OUT Programmable Output Voltage

ANY-OUT PROGRAM PINS (Active Low)	ADDITIVE OUTPUT VOLTAGE LEVEL
Pin 4 (6P4V2)	6.4 V
Pin 5 (6P4V1)	6.4 V
Pin 6 (3P2)	3.2 V
Pin 8 (1P6)	1.6 V
Pin 9 (0P8)	800 mV
Pin 10 (0P4)	400 mV
Pin 11 (0P2)	200 mV
Pin 12 (0P1)	100 mV

Table 2 shows a list of the most common output voltages and the corresponding pin settings. The voltage setting pins have a binary weight; therefore, the output voltage can be programmed to any value from 1.4 V to 20.5 V in 100-mV steps.

Table 2. Common Output Voltages and Corresponding Pin Settings

V_O (V)	PIN NAMES AND VOLTAGE PER PIN
V_O (V)	0P1V (100 mV)	0P2V (200 mV)	0P4V (400 mV)	0P8V (800 mV)	1P6V (1.6 V)	3P2V (3.2 V)	6P4V1 (6.4 V)	6P4V2 (6.4 V)
1.4	Open	Open	Open	Open	Open	Open	Open	Open
1.5	GND	Open	Open	Open	Open	Open	Open	Open
1.8	Open	Open	GND	Open	Open	Open	Open	Open
2.5	GND	GND	Open	GND	Open	Open	Open	Open
3	Open	Open	Open	Open	GND	Open	Open	Open
3.3	GND	GND	Open	Open	GND	Open	Open	Open
4.5	GND	GND	GND	GND	GND	Open	Open	Open
5	Open	Open	GND	Open	Open	GND	Open	Open
10	Open	GND	GND	Open	GND	Open	GND	Open
12	Open	GND	Open	GND	Open	GND	GND	Open
15	Open	Open	Open	GND	Open	Open	GND	GND
18	Open	GND	GND	Open	Open	GND	GND	GND
20.5	GND	GND	GND	GND	GND	GND	GND	GND

7.5.2 Adjustable Operation

The TPS7A47-Q1 has an output voltage range of 1.4 V to 34 V. For adjustable operation, set the nominal output voltage of the device (as shown in Figure 23) using two external resistors.

Figure 23. Adjustable Operation for Maximum AC Performance

R₁ and R₂ can be calculated for any output voltage within the operational range. The current through feedback resistor R₂ must be at least 5 µA to ensure stability. Additionally, the current into the FB pin (I_(FB), typically 350 nA) creates an additional output voltage offset that depends on the resistance of R₁. For high-accuracy applications, select R₂ such that the current through R₂ is at least 35 µA to minimize any effects of I_(FB) variation on the output voltage; 10 kΩ is recommended. Equation 3 calculates R₁.

Equation 3. TPS7A47-Q1 q_r1_bvs204.gif

where

V_REF = 1.4 V
I_FB = 350 nA

Use 0.1% tolerance resistors to minimize the effects of resistor inaccuracy on the output voltage.

Table 3 shows the resistor combinations to achieve some standard rail voltages with commercially available 1% tolerance resistors. The resulting output voltages yield a nominal error of < 0.5%.

Table 3. Suggested Resistors for Common Voltage Rails

V_OUT	R₁, CALCULATED	R₁, CLOSEST 1% VALUE	R₂
1.4 V	0 Ω	0 Ω	∞
1.8 V	2.782 kΩ	2.8 kΩ	9.76 kΩ
3.3 V	13.213 kΩ	13.3 kΩ	9.76 kΩ
5 V	25.650 kΩ	25.5 kΩ	10 kΩ
12 V	77.032 kΩ	76.8 kΩ	10.2 kΩ
15 V	101.733 kΩ	102 kΩ	10.5 kΩ
18 V	118.276 kΩ	118 kΩ	10 kΩ
24 V	164.238 kΩ	165 kΩ	10.2 kΩ

To achieve higher nominal accuracy, two resistors can be used in the place of R₁. Select the two resistor values such that the sum results in a value as close as possible to the calculated R₁ value.

There are several alternative ways to set the output voltage. The program pins can be pulled low using external general-purpose input/output pins (GPIOs), or can be hardwired by the given layout of the printed circuit board (PCB) to set the ANY-OUT voltage. The TPS7A4701 evaluation module (EVM), available for purchase from the TI eStore, allows the output voltage to be programmed using jumpers.