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  • TPS7A57 5-A, Low-VIN (0.7 V), Low-Noise (2.1 μVRMS), High-Accuracy (1%), Ultra-Low Dropout (LDO) Voltage Regulator

    • SBVS395 July   2022 TPS7A57

      PRODUCTION DATA  

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  • TPS7A57 5-A, Low-VIN (0.7 V), Low-Noise (2.1 μVRMS), High-Accuracy (1%), Ultra-Low Dropout (LDO) Voltage Regulator
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Soft-Start (NR/SS Pin)
      4. 7.3.4 Precision Enable and UVLO
      5. 7.3.5 Charge Pump Enable and BIAS Rail
      6. 7.3.6 Power-Good Pin (PG Pin)
      7. 7.3.7 Active Discharge
      8. 7.3.8 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Precision Enable (External UVLO)
      2. 8.1.2  Undervoltage Lockout (UVLO) Operation
        1. 8.1.2.1 IN Pin UVLO
        2. 8.1.2.2 BIAS UVLO
        3. 8.1.2.3 Typical UVLO Operation
        4. 8.1.2.4 UVLO(IN) and UVLO(BIAS) Interaction
      3. 8.1.3  Dropout Voltage (VDO)
      4. 8.1.4  Input and Output Capacitor Requirements (CIN and COUT)
      5. 8.1.5  Recommended Capacitor Types
      6. 8.1.6  Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)
      7. 8.1.7  Optimizing Noise and PSRR
      8. 8.1.8  Adjustable Operation
      9. 8.1.9  Load Transient Response
      10. 8.1.10 Current Limit and Foldback Behavior
      11. 8.1.11 Charge Pump Operation
      12. 8.1.12 Sequencing
      13. 8.1.13 Power-Good Functionality
      14. 8.1.14 Output Impedance
      15. 8.1.15 Paralleling for Higher Output Current and Lower Noise
      16. 8.1.16 Current Mode Margining
      17. 8.1.17 Voltage Mode Margining
      18. 8.1.18 Power Dissipation (PD)
      19. 8.1.19 Estimating Junction Temperature
      20. 8.1.20 TPS7A57EVM-081 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data
  11. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RTE|16
    • MPQF149D
Thermal pad, mechanical data (Package|Pins)
  • RTE|16
    • QFND525B
Orderable Information
  • sbvs395_oa
  • sbvs395_pm
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DATA SHEET

TPS7A57 5-A, Low-VIN (0.7 V), Low-Noise (2.1 μVRMS), High-Accuracy (1%), Ultra-Low Dropout (LDO) Voltage Regulator

1 Features

  • Input voltage range:
    • Without BIAS: 1.1 V to 6.0 V
    • With BIAS: 0.7 V to 6.0 V
  • Output voltage noise: 2.45 μVRMS
  • 1% (max) accuracy over line, load, and temperature
  • Low dropout: 75 mV at 5 A
  • Power-supply rejection ratio (5 A):
    • 100 dB at 1 kHz
    • 78 dB at 10 kHz
    • 60 dB at 100 kHz
    • 36 dB at 1 MHz
  • Superior load transient response:
    • ±2 mV with a 100-mA to 5-A load step
  • Adjustable output voltage range: 0.5 V to 5.2 V
  • Adjustable soft-start inrush control
  • BIAS rail:
    • Internal charge pump or 3-V to 11-V external rail
    • Internal charge pump can be disabled
  • Open-drain, power-good (PG) output
  • Package: 3-mm × 3-mm, 16-pin WQFN
    • EVM RθJA: 21.9°C/W

2 Applications

  • Macro remote radio units (RRU)
  • Outdoor backhaul units
  • Active antenna system mMIMO (AAS)
  • Ultrasound scanners
  • Lab and field instrumentation
  • Sensor, imaging, and radar

3 Description

The TPS7A57 is a low-noise (2.45 µVRMS), ultra-low-dropout linear regulator (LDO) capable of sourcing 5 A with only 75 mV of dropout, independently of the output voltage. The device output voltage is adjustable from 0.5 V to 5.2 V using a single external resistor. The combination of low noise, high PSRR (36 dB at 1 MHz), and high output-current capability makes the TPS7A57 designed for powering noise-sensitive components (such as RF amplifiers, radar sensors, SERDES and analog chipsets) found in radar power, communication, and imaging applications.

Digital loads [such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs)] requiring low-input, low-output (LILO) voltage operation also benefit from the exceptional accuracy (1% over load, line, and temperature), remote sensing, excellent transient performance, and soft-start capabilities to provide optimal system performance. The versatility, performance, and small footprint solution make this LDO an excellent choice for high-current analog loads such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and imaging sensors as well as digital loads such as serializer/deserializers (SerDes), FPGAs, and DSPs.

Package Information(1)
PART NUMBERPACKAGEBODY SIZE (NOM)
TPS7A57WQFN (16)3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20211102-SS0I-6Q48-PCBF-2GXSVHLCDCPF-low.gifTypical Application Circuit
GUID-20220504-SS0I-LM6C-GFN2-MN6RN5KXM6DT-low.png5-A, 1.2VIN, 0.9-VOUT PSRR With CP Enabled

4 Revision History

DATE REVISION NOTES
July 2022 * Initial release

5 Pin Configuration and Functions

Figure 5-1 RTE Package,16-Pin WQFN(Top View)
Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
BIAS 5 I

BIAS supply voltage pin. See the Section 7.3.5 section for additional information.
CP_EN 15 I Charge pump enable pin. See the Section 7.3.5 section for additional information.
EN 16 I Enable pin. See the Section 7.3.4 section for additional information.
GND 6 GND Ground pin. See the Section 8.4.1 section for additional information.
IN 1, 2, 3, 4 I Input supply voltage pin. See the Section 8.1.4 section for more details.
NR/SS 8 I/O

Noise-reduction pin. See the Section 7.3.3 and Section 8.1.6 sections for additional information.
OUT 9, 10, 11, 12 O Regulated output pin. See the Section 7.3.1 and Section 8.1.4 sections for more details.
PG 14 O Open-drain, power-good indicator pin for the low-dropout regulator (LDO) output voltage. See the Section 7.3.6 section for additional information.
REF 7 I/O Reference pin. See the Section 7.3.1 section for additional information.
SNS 13 I Output sense pin. See the Section 7.3.1 section for additional information.
Thermal Pad — GND Connect the pad to GND for best possible thermal performance. See the Section 8.4 section for more information.
(1) I = input, O = output, I/O = input or output, G = ground.

 
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