The TPS7A8101-Q1 low-dropout linear regulator (LDO) offers very good performance in output noise and power-supply rejection ratio (PSRR). This LDO uses an advanced BiCMOS process and a PMOSFET pass device to achieve very low noise, excellent transient response, and excellent PSRR performance.
The TPS7A8101-Q1 device is stable with a 4.7-μF ceramic output capacitor and uses a precision voltage reference and feedback loop to achieve a worst-case accuracy of 3% over all load, line, process, and temperature variations.
This device is fully specified over the temperature range of TA = –40°C to 125°C and is offered in a
3-mm × 3-mm, SON-8 package with a thermal pad.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS7A8101-Q1 | SON (8) | 3.00 mm × 3.00 mm |
Changes from * Revision (April 2014) to A Revision
PIN | DESCRIPTION | |
---|---|---|
NAME | NO. | |
EN | 5 | Driving this pin high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. See to the Shutdown section for more details. The EN pin must not be left floating and can be connected to the IN pin if not used. |
FB/SNS | 3 | This pin is the input to the error amplifier and is used to set the output voltage of the device. |
GND | 4 | Ground |
IN | 7 | Unregulated input supply |
8 | ||
NR | 6 | Connect an external capacitor between this pin and ground to reduce output noise to very low levels. The capacitor also slows down the VO ramp (RC soft start). |
OUT | 1 | Regulator output. A 4.7-μF or larger ceramic capacitor is required for stability. |
2 | ||
Thermal Pad | — | The Thermal Pad should be connected to GND. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | IN | –0.3 | 7 | V |
FB/SNS, NR | –0.3 | 3.6 | V | |
EN | –0.3 | VI + 0.3(2) | V | |
OUT | –0.3 | 7 | V | |
Current | OUT | Internally Limited | A | |
Operating junction temperature, TJ | –55 | 150 | °C |
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
Tstg | Storage temperature range | –55 | 150 | °C | ||
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002, classification level H2(1) | –2 | 2 | kV | |
Charged device model (CDM), per JEDEC specification JESD22-C101, classification level C4B | Corner pins (1, 4, 5, and 8) |
–750 | 750 | V | ||
Other pins | –500 | 500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VI | Input voltage | 2.2 | 6.5 | V |
IO | Output current | 0 | 1 | A |
TA | Operating free air temperature | –40 | 125 | °C |
THERMAL METRIC(1) | DRB | UNIT | |
---|---|---|---|
(8 PINS) | |||
RθJA | Junction-to-ambient thermal resistance | 45.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 53.1 | |
RθJB | Junction-to-board thermal resistance | 21.2 | |
ψJT | Junction-to-top characterization parameter | 0.9 | |
ψJB | Junction-to-board characterization parameter | 21.4 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 5.2 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
VI | Input voltage range(1) | 2.2 | 6.5 | V | ||||
V(NR) | Internal reference | 0.79 | 0.8 | 0.81 | V | |||
VO | Output voltage range | 0.8 | 6 | V | ||||
Output accuracy(2) | VO + 0.5 V ≤ VI ≤ 6 V, VI ≥ 2.5 V, 100 mA ≤ IO ≤ 500 mA, 0°C ≤ TJ ≤ 85°C |
–2% | 2% | |||||
VO + 0.5 V ≤ VI ≤ 6.5 V, VI ≥ 2.2 V, 100 mA ≤ IO ≤ 1 A |
–3% | ±0.3% | 3% | |||||
ΔVO(ΔVI) | Line regulation | VOnom + 0.5 V ≤ VI ≤ 6.5 V, VI ≥ 2.2 V, IO = 100 mA |
150 | μV/V | ||||
ΔVO(ΔIL) | Load regulation | 100 mA ≤ IO ≤ 1 A | 2 | μV/mA | ||||
VDO | Dropout voltage(3) | VO + 0.5 V ≤ VI ≤ 6.5 V, VI ≥ 2.2 V, IO = 500 mA, V(FB/SNS) = GND |
250 | mV | ||||
VO + 0.5 V ≤ VI ≤ 6.5 V, VI ≥ 2.5 V, IO = 750 mA, V(FB/SNS) = GND |
350 | mV | ||||||
VO + 0.5 V ≤ VI ≤ 6.5 V, VI ≥ 2.5 V, IO = 1 A, V(FB/SNS) = GND |
500 | mV | ||||||
IL | Output current-limit | VO = 0.85 × VOnom, VI ≥ 3.3 V | 1100 | 1400 | 2000 | mA | ||
I(GND) | Ground pin current | IO = 1 mA | 60 | 100 | μA | |||
IO = 1 A | 350 | μA | ||||||
IL(sd) | Shutdown current (I(GND)) | V(EN) ≤ 0.4 V, VI ≥ 2.2 V, RL = 1 kΩ, 0°C ≤ TJ ≤ 125°C |
0.2 | 2.5 | μA | |||
I(FB/SNS) | Feedback pin current | VI = 6.5 V, V(FB/SNS) = 0.8 V | 0.02 | 1 | μA | |||
PSRR | Power-supply rejection ratio | VI = 4.3 V, VO = 3.3 V, IO = 750 mA |
ƒ = 100 Hz | 80 | dB | |||
ƒ = 1 kHz | 82 | dB | ||||||
ƒ = 10 kHz | 78 | dB | ||||||
ƒ = 100 kHz | 60 | dB | ||||||
ƒ = 1 MHz | 54 | dB | ||||||
Vn | Output noise voltage | BW = 100 Hz to 100 kHz, VI = 3.8 V, VO = 3.3 V, IO = 100 mA, C(NR) = C(BYPASS) = 470 nF |
23.5 | μVRMS | ||||
V(EN)H | Enable high (enabled) | 2.2 V ≤ VI ≤ 3.6 V, RL = 1 kΩ | 1.2 | V | ||||
3.6 V < VI ≤ 6.5 V, RL = 1 kΩ | 1.35 | V | ||||||
V(EN)L | Enable low (shutdown) | RL = 1 kΩ | 0 | 0.4 | V | |||
I(EN) | Enable pin current, enabled | VI = V(EN) = 6.5 V | 0.02 | 1 | μA | |||
tst | Startup time | VOnom = 3.3 V, VO = 0% to 90% VOnom, R1 = 3.3 kΩ, C(OUT) = 10 μF, C(NR) = 470 nF |
80 | ms | ||||
UVLO | Undervoltage lockout | VI rising, RL = 1 kΩ | 1.86 | 2 | 2.1 | V | ||
Hysteresis | VI falling, RL = 1 kΩ | 75 | mV | |||||
Tsd | Thermal shutdown temperature | Shutdown, temperature increasing | 160 | °C | ||||
Reset, temperature decreasing | 140 | °C |
NOTE: The Y-axis shows 1% VO per division | ||
VO = 0.8 V | IO = 750 mA | |
NOTE: The Y-axis shows 1% VO per division |
IO = 1 A | ||
IO = 500 mA | ||
VI = 3.6 V | ||
VO = VI – 0.5 V |
VI – VO = 1 V | C(IN) = 0 F | C(OUT) = 10 µF |
C(NR) = C(BYPASS) = 470 nF |
VI – VO = 1 V | C(IN) = 0 F | C(OUT) = 10 µF |
C(NR) = C(BYPASS) = 470 nF |
IO = 100 mA | C(IN) = 0 F |
VI – VO = 0.5 V | C(OUT) = 10 µF | C(IN) = 10 µF | |
24.09 µVRMS (C(NR) = C(BYPASS) = 100 nF) | |||
23.54 µVRMS (C(NR) = C(BYPASS) = 470 nF) |
23.54 µVRMS (IO = 100 mA) | C(IN) = 10 µF | VI – VO = 0.5 V |
23.71 µVRMS (IO = 750 mA) | C(NR) = 470 nF | C(OUT) = 10 µF |
22.78 µVRMS (IO = 1 A) | C(BYPASS) = 470 nF |
Using the same value of C(NR) and C(BYPASS) in the X-Axis |
IO = 100 mA → 1 A → 100 mA | ||
RL = 33 Ω | C(NR) = 470 nF | C(BYPASS) = 470 nF | ||
C(OUT) = 10 µF | C(IN) = 10 µF | |||
(1) The internal reference requires approximately 80 ms of rampup time (see Startup) from the enable event; therefore, VO fully reaches the target output voltage of 3.3 V in 80 ms from startup. |
NOTE: The Y-axis shows 1% VO per division | ||
VO = 0.8 V | IO = 5 mA | |
NOTE: The Y-axis shows 1% VO per division |
IO = 750 mA | ||
VI = 3.6 V | ||
VO = 0.8 V | IO = 750 mA | |
V(EN) = 0.4 V | ||
C(NR) = C(BYPASS) = 470 nF | C(OUT) = 10 µF | C(IN) = 0 F |
VI – VO = 0.5 V | C(IN) = 0 F | C(OUT) = 10 µF |
C(NR) = C(BYPASS) = 470 nF |
VI – VO = 0.5 V | C(IN) = 0 F | C(OUT) = 10 µF |
C(NR) = C(BYPASS) = 470 nF |
IO = 750 mA | C(IN) = 0 F |
25.89 µVRMS (VO = 1.8 V) | C(IN) = 10 µF | VI – VO = 0.5 V |
23.54 µVRMS (VO = 2.5 V) | C(NR) = 470 nF | C(OUT) = 10 µF |
23.54 µVRMS (VO = 3.3 V) | C(BYPASS) = 470 nF |
23.54 µVRMS (CO = 10 µF) | C(IN) = 10 µF | VI – VO = 0.5 V |
23.91 µVRMS (CO = 22 µF) | C(NR) = 470 nF | C(OUT) = 10 µF |
22.78 µVRMS (CO = 100 µF) | C(BYPASS) = 470 nF |
VI = 3.8 V → 4.8 V → 3.8 V | ||
IO = 500 mA |
RL = 33 Ω | C(NR) = 470 nF | C(BYPASS) = 470 nF |
C(OUT) = 10 µF | C(IN) = 10 µF |