The TPS92691/-Q1 is a versatile LED controller that can support a range of step-up or step-down driver topologies. The device implements a fixed-frequency peak current mode control technique with programmable switching frequency, slope compensation, and soft-start timing. It incorporates a high voltage (65-V) rail-to-rail current sense amplifier that can directly measure LED current using either a high-side or a low-side series sense resistor. The amplifier is designed to achieve low input offset voltage and attain better than ±3% LED current accuracy over junction temperature range of 25°C to 140°C and output common-mode voltage range of 0 to 60 V.
LED current can be independently modulated using either analog or PWM dimming techniques. Linear analog dimming response with 15:1 range is obtained by varying the voltage from 140 mV to 2.25 V across the high impedance analog adjust (IADJ) input. PWM dimming of LED current is achieved by modulating the PWM input pin with the desired duty cycle and frequency. Optional DDRV gate driver output can be used to enable series FET dimming functionality to get over 1000:1 contrast ratio.
The TPS92691/-Q1 supports continuous LED status check through the current monitor (IMON) output. This allows for LED short circuit or open circuit detection and protection. Additional fault protection features include VCC UVLO, output OVP, switch cycle-by-cycle current limit, and thermal protection.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS92691-Q1 TPS92691 |
HTSSOP (16) | 5.10 mm × 6.60 mm |
DATE | REVISION | NOTES |
---|---|---|
December 2015 | * | Initial release. |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VIN | — | Input supply for the internal VCC regulator. Bypass with 100-nF capacitor to GND located close to the controller. |
2 | SS | I/O | Soft-start programming pin. Connect a capacitor to AGND to extend the start-up time. Switching can be disabled by shorting the pin to GND. |
3 | RT/SYNC | I/O | Oscillator frequency programming pin. Connect a resistor to AGND to set the switching frequency. The internal oscillator can be synchronized by coupling an external clock pulse through 100-nF series capacitor. |
4 | PWM | I | PWM dimming input. Driving the pin below 2.3 V (typ), turns off switching, idles the oscillator, disconnects the COMP pin, and sets DDRV output to ground. The input signal duty cycle controls the average LED current through PWM dimming operation. Connect to VCC when not used for PWM dimming. |
5 | COMP | I/O | Transconductance error amplifier output. Connect compensation network to achieve desired closed-loop response. |
6 | IADJ | I | LED current reference input. Connecting pin to VCC with 100-kΩ series resistor sets internal reference voltage to 2.42 V and the current sense threshold, V(CSP-CSN)to 172 mV. The pin can be modulated by external voltage source from 0 V to 2.25 V to implement analog dimming. |
7 | IMON | O | LED current report pin. The LED current sensed by CSP/CSN input is reported as VIMON = 14 × ILED × Rcs. Bypass with a 1-nF ceramic capacitor to AGND. |
8 | AGND | — | Analog ground. Return for the internal voltage reference and analog circuit. Connect to circuit ground, GND, to complete return path. |
9 | CSN | I | Current sense amplifier negative input (–). Connect directly to the negative node of LED current sense resistor RCS). |
10 | CSP | I | Current sense amplifier positive input (+). Connect directly to the positive node of LED current sense resistor RCS). |
11 | DDRV | O | Series dimming FET gate driver output. Connect to gate of external N-channel MOSFET or a level-shift circuit with P-channel MOSFET to implement series FET PWM dimming. |
12 | OVP | I | Hysteretic overvoltage protection input. Connect resistor divider from output voltage to set OVP threshold and hysteresis. |
13 | PGND | — | Power ground connection pin for internal N-channel MOSFET gate drivers. Connect to circuit ground, GND, to complete return path. |
14 | IS | I | Switch current sense input. Connected to the switch current sense resistor, RIS, in the source of the N-channel MOSFET. |
15 | GATE | O | N-channel MOSFET gate driver output. Connect to gate of external switching N-channel MOSFET. |
16 | VCC | — | VCC bias supply pin. Locally decouple to PGND using a 2.2-µF to 4.7-µF ceramic capacitor located close to the controller. |
PowerPAD | — | The AGND and PGND pin must be connected to the exposed PowerPAD for proper operation. This PowerPAD must be connected to PCB ground plane using multiple vias for good thermal performance. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VIN, CSP, CSN | –0.3 | 65 | V |
IADJ, IS, PWM, RT/SYNC | –0.3 | 8.8 | V | |
OVP, SS | –0.3 | 5.5 | V | |
CSP to CSN(3), PGND | –0.3 | 0.3 | V | |
Output voltage(4) | VCC, GATE, DDRV | –0.3 | 8.8 | V |
COMP | –0.3 | 5.0 | V | |
Source current | IMON | — | 100 | µA |
GATE, DDRV (Pulsed <20 ns) | — | 500 | mA | |
Sink current | GATE, DDRV (Pulsed <20 ns) | — | 500 | mA |
Operating junction temperature, TJ | –40 | 140 | °C | |
Storage temperature, Tstg | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
TPS92691-Q1 IN PWP (HTSSOP) PACKAGE | |||||
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002, all pins(1) | ±2000 | V | |
Charged-device model (CDM), per AEC Q100-011 | All pins except 1, 8, 9, and 16 | ±500 | |||
Pins 1, 8, 9, and 16 | ±750 | ||||
TPS92691 IN PWP (HTSSOP) PACKAGE | |||||
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2) | ±2000 | V | |
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(3) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | Supply input voltage | 6.5 | 14 | 65 | V |
VIN, crank | Supply input, battery crank voltage | 4.5 | V | ||
VCSP, VCSN | Current sense common mode | 0 | 60 | V | |
ƒSW | Switching frequency | 80 | 700 | kHz | |
ƒSYNC | SYNC frequency | 0.8 × ƒsw | 1.2 × ƒSW | kHz | |
VIADJ | Current reference voltage | 0.14 | VIADJ(CLAMP) | V | |
TA | Operating ambient temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS92691/-Q1 | UNIT | |
---|---|---|---|
PWP (HTSSOP) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 40.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 26.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 22.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.8 | °C/W |
ψJB | Junction-to-board characterization parameter | 22.0 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.3 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT VOLTAGE (VIN) | ||||||
VDO | LDO dropout voltage | ICC = 20 mA, VIN = 5 V | 300 | mV | ||
BIAS SUPPLY (VCC) | ||||||
VCC(REG) | Regulation voltage | No load | 7.0 | 7.5 | 8.0 | V |
VCC(UVLO) | Supply undervoltage protection | VCC rising threshold, VIN = 8 V | 4.1 | 4.35 | V | |
VCC falling threshold, VIN = 8 V | 3.75 | 4.0 | V | |||
Hysteresis | 100 | mV | ||||
ICC(LIMIT) | Supply current limit | VCC = 0 V | 26 | 38 | 46 | mA |
ICC(STBY) | Supply stand-by current | VPWM = 0 V | 1.8 | 2.1 | mA | |
ICC(SW) | Supply switching current | VCC = 7.5 V, CGATE = 1 nF | 5.1 | 6.6 | mA | |
OSCILLATOR (RT/SYNC) | ||||||
ƒSW | Switching frequency | RT = 40 kΩ | 165 | 200 | 230 | kHz |
RT = 20 kΩ | 327 | 390 | 448 | kHz | ||
VRT | RT output voltage | 1 | V | |||
VSYNC | SYNC rising threshold | VRT/SYNC rising | 2.7 | 3.1 | V | |
SYNC falling threshold | VRT/SYNC falling | 1.8 | 2 | V | ||
tSYNC(MIN) | Minimum SYNC clock pulse width | 100 | ns | |||
GATE DRIVER (GATE) | ||||||
RGH | Gate driver high side resistance | IGATE = –10 mA | 5.4 | 11.2 | Ω | |
RGL | Gate driver low side resistance | IGATE = 10 mA | 4.3 | 10.5 | Ω | |
CURRENT SENSE (IS) | ||||||
VIS(LIMIT) | Current limit threshold | 497 | 525 | 550 | mV | |
tIS(BLANK) | Leading edge blanking time | 103 | 150 | 188 | ns | |
tIS(FAULT) | Current limit fault time | 35 | µs | |||
tILMT(DLY) | IS to GATE propagation delay | VIS pulsed from 0 to 1 V | 100 | ns | ||
PWM COMPARATOR AND SLOPE COMPENSATION | ||||||
DMAX | Maximum duty cycle | 90.4% | 93% | 94.7% | ||
VLV | IS to COMP level shift voltage | No slope compensation added | 1.17 | 1.5 | 1.8 | V |
VSL | Slope compensation | D = DMAX (with max slope compensation) | 200 | mV | ||
ILV | IS level shift bias current | No slope compensation added | 25 | µA | ||
ILV + ISL | IS level shift source current | D = DMAX (with max slope compensation) | 115 | µA | ||
CURRENT SENSE AMPLIFIER (CSP, CSN) | ||||||
VCS(offset) | Cumulative offset voltage at VCSP = 60 V and V(CSP-CSN) = 150 mV, referred to current sense input | –40°C ≤ TJ ≤ 140°C | –5.2 | 5.9 | mV | |
25°C ≤ TJ ≤ 140°C | –4.4 | 4.6 | mV | |||
Cumulative offset voltage at VCSP = 60 V and V(CSP-CSN) = 10 mV, referred to current sense input | –40°C ≤ TJ ≤ 140°C | –3.5 | 5.0 | mV | ||
25°C ≤ TJ ≤ 140°C | -2.8 | 4.0 | mV | |||
Cumulative offset voltage at VCSN = 0 V and V(CSP-CSN) = 150 mV, referred to current sense input | –40°C ≤ TJ ≤ 140°C | –5.9 | 6.7 | mV | ||
25°C ≤ TJ ≤ 140°C | -4.7 | 5.0 | mV | |||
Cumulative offset voltage at VCSN = 0 V and V(CSP-CSN) = 10 mV, referred to current sense input | –40°C ≤ TJ ≤ 140°C | –2.3 | 3.2 | mV | ||
25°C ≤ TJ ≤ 140°C | –1.7 | 2.6 | mV | |||
CS(BW) | Current sense unity gain bandwidth | 500 | kHz | |||
ICS(BIAS) | CSP, CSN bias current | VCSP, CSN = 60 V | 4 | µA | ||
CURRENT MONITOR (IMON) | ||||||
VIMON(CLP) | IMON output voltage clamp | 3.2 | 3.7 | 4.2 | V | |
VIMON(OS) | IMON buffer offset voltage | –11.4 | –1.6 | 7.3 | mV | |
ANALOG ADJUST (IADJ) | ||||||
VIADJ(CLP) | IADJ internal clamp voltage | IIADJ = 1 µA | 2.27 | 2.42 | 2.55 | V |
IIADJ(BIAS) | IADJ input bias current | VIADJ < 2.2 V | 90 | nA | ||
RIADJ(LMT) | IADJ current limiting series resistor | VIADJ > 2.6 V | 12 | kΩ | ||
ERROR AMPLIFIER (COMP) | ||||||
gM | Transconductance | 121 | µA/V | |||
ICOMP(SRC) | COMP current source capacity | VIADJ = 1.4 V, V(CSP-CSN) = 0 V | 130 | µA | ||
ICOMP(SINK) | COMP current sink capacity | VIADJ = 0 V, V(CSP-CSN) = 0.1 V | 130 | µA | ||
EA(BW) | Error amplifier bandwidth | –3 dB | 5 | MHz | ||
VCOMP(RST) | COMP pin reset voltage | 100 | mV | |||
RCOMP(DCH) | COMP discharge FET resistance | 246 | Ω | |||
SOFT-START (SS) | ||||||
ISS | Soft-start source current | 7 | 10 | 12.8 | µA | |
VSS(RST) | Soft-start pin reset voltage | 25 | mV | |||
RSS(DCH) | SS discharge FET resistance | 260 | Ω | |||
OVERVOLTAGE PROTECTION (OVP) | ||||||
VOVP(THR) | OVP detection threshold | 1.18 | 1.24 | 1.31 | V | |
IOVP(HYS) | OVP hysteresis current | 12 | 20 | 27.5 | µA | |
PWM INPUT (PWM) | ||||||
VPWM(HIGH) | Schmitt trigger logic level (high threshold) | 2.5 | 2.7 | V | ||
VPWM(LOW) | Schmitt trigger logic level (low threshold) | 2.0 | 2.3 | V | ||
RPWM(PD) | PWM pulldown resistance | 1 | MΩ | |||
tDLY(RISE) | PWM to DDRV rising delay | 54 | ns | |||
tDLY(FALL) | PWM to DDRV falling delay | 72 | ns | |||
PWM GATE DRIVE OUTPUT (DDRV) | ||||||
RDH | DDRV high-side resistance | 6.1 | 12.8 | Ω | ||
RDL | DDRV low-side resistance | 5.2 | 11.4 | Ω | ||
THERMAL SHUTDOWN | ||||||
Thermal shutdown temperature | 175 | °C | ||||
Thermal shutdown hysteresis | 25 | °C |
VIADJ = 2.1 V |
VIADJ = 2.1 V |
The TPS92691/-Q1 wide input range (4.5 V to 65 V) controller features all of the functions necessary to implement a highly efficient and compact LED driver based on step-up or step-down converter topologies. The device implements a fixed-frequency, peak current mode control technique to achieve a constant current output, ideal for driving a single string of series-connected LEDs. The integrated low input offset, rail-to-rail current sense amplifier supports a wide range of output voltages (0 V to 65 V) and is capable of powering an LED string consisting of 1 to more than 20 white LEDs. The controller is compatible with either high- or low-side current shunt sensing technique, based on the LED configuration and driver topology. The LED current sense threshold, set by the analog adjust input, IADJ, provides the capability to analog (amplitude) dim over a linear range of 15:1 by varying the voltage, VIADJ, from 140 mV to 2.25 V. The IADJ input provides the means to externally program LED current and facilitates calibration, brightness correction, and thermal management of the LEDs. High resolution and linear dimming response is achieved by varying the duty cycle of LED current based on the PWM input. The PWM input directly controls the GATE and DDRV drive outputs, controls the internal oscillator, and enables high-speed PWM dimming with over 1000:1 contrast ratio when using an external MOSFET placed in series with the LED load. The current monitor output, IMON, reports the instantaneous status of LED current measured by the rail-to-rail current sense amplifier. This feature is incorporated to indicate LED short and open-circuit failures and enables cable harness fault detection independent of LED driver topology. Other fault protection features include cycle-by-cycle current limiting, hysteresis-based overvoltage protection, VCC undervoltage protection, thermal shutdown, and remote shutdown capability by pulling down the SS pin.
The IC incorporates a 65-V input VIN rated linear regulator to generate the 7.5 V (typ) VCC bias supply and other internal reference voltages. The VCC output is monitored to implement UVLO protection. The device is enabled when VCC exceeds the 4.1-V (typ) threshold and is disabled when VCC drops below the 4.0-V (typ) threshold. The UVLO comparator provides 0.1 V of hysteresis to avoid chatter during transitions. The UVLO thresholds are internally fixed and cannot be adjusted. The supply current, ICC, is limited to 26 mA minimum to protect the device under VCC pin short-circuit conditions. The VCC supply powers the internal circuitry and N-channel gate driver outputs, GATE, and DDRV. Place a bypass capacitor in the range of 2.2 µF to 4.7 µF across the VCC output and PGND to ensure proper operation. The regulator operates in dropout when input voltage VIN falls below 7.5 V forcing VCC to be lower than VIN by 300 mV for a 20-mA supply current. The VCC is a regulated output of the internal regulator and is not recommended to be driven from an external power supply.
The TPS92691/-Q1 switching frequency is programmable by a single external resistor connected between the RT/SYNC pin and the AGND pin. To set a desired frequency, ƒSW (Hz), the resistor value can be calculated from Equation 1.
Figure 6 shows a graph of switching frequency versus resistance, RT. TI recommends a switching frequency setting between 80 kHz and 700 kHz for optimal performance over input and output voltage operating range and for best efficiency. Operation at higher switching frequencies requires careful selection of N-channel MOSFET characteristics and should take into consideration additional switching losses and junction temperature rise.
The internal oscillator can be synchronized by AC coupling an external clock pulse to RT/SYNC pin as shown in Figure 19. The positive going synchronization clock at the RT pin must exceed the RT sync threshold and the negative going synchronization clock at the RT pin must exceed the RT sync falling threshold to trip the internal synchronization pulse detector. TI recommends that the frequency of the external synchronization pulse is within ±20% of the internal oscillator frequency programmed by the RT resistor. TI recommends a minimum coupling capacitor of 100 nF and typical pulse width of 100 ns for proper synchronization. In the case where external synchronization clock is lost the internal oscillator takes control of the switching rate based on the RT resistor to maintain output current regulation. The RT resistor is always required whether the oscillator is free running or externally synchronized.
The TPS92691/-Q1 contains a N-channel gate driver that switches the output VGATE between VCC and PGND. A peak source and sink current of 500 mA allows controlled slew-rate of the MOSFET gate and drain node voltages, limiting the conducted and radiated EMI generated by switching. The gate driver supply current ICC(GATE) depends on the total gate drive charge (QG) of the MOSFET and the operating frequency of the converter, ƒSW, . TI recommends a MOSFET with a low gate charge specification to limit the junction temperature rise and switch transition losses.
While choosing the N-channel MOSFET device, consider the threshold voltage when operating in the dropout region when VIN is below the VCC regulation level. TI recommends a logic level device with a threshold voltage below 5 V when the device is required to operate at an input voltage less than 7 V.
The internal rail-to-rail current sense amplifier measures the average LED current based on the differential voltage drop between the CSP and CSN inputs over a common mode range of 0 V to 65 V. The differential voltage, V(CSP-CSN), is amplified by a voltage-gain factor of 14 and is connected to the negative input of the transconductance error amplifier. Accurate LED current feedback is achieved by limiting the cumulative input offset voltage, (represented by the sum of the voltage-gain error, the intrinsic current sense offset voltage, and the transconductance error amplifier offset voltage) to less than 5 mV over the recommended common-mode voltage, and temperature range.
An optional common-mode or differential mode low-pass filter implementation, as shown in Figure 20, can be used to smooth out the effects of large output current ripple and switching current spikes caused by diode reverse recovery. TI recommends a filter resistance in the range of 10 Ω to 100 Ω to limit the additional offset caused by amplifier bias current and achieve best accuracy and line regulation.
The internal transconductance amplifier generates an error signal proportional to the difference between the LED current sense feedback voltage and the external IADJ input voltage. Closed-loop regulation is achieved by connecting a compensation network to the output of the error amplifier. In most LED driver applications, a stable response can be achieved by connecting a capacitor across the COMP output and ground to implement a simple integral compensator. TI recommends a capacitor value between 10 nF and 100 nF as a good starting point. Higher closed-loop bandwidth can be achieved by implementing a proportional-integral compensator consisting of a series resistor and a capacitor network connected across the COMP output and ground. Based on the converter topology, the compensation network should be tuned to achieve a minimum of 60° of phase margin and 10 dB of gain margin. The Application and Implementation section presents detailed equations.
The main MOSFET current is monitored by the IS input pin to implement peak current mode control. The GATE output duty cycle is derived by comparing the peak switch current, measured by the RIS resistor, to the internal COMP voltage threshold. An internal slope signal is added to the measured sense voltage, VIS, to prevent subharmonic oscillations for duty cycles greater than 50%. The linear slope voltage, VSL, of fixed amplitude 200 mV, is derived from a 100-µA sawtooth ramp current synchronized to the internal oscillator frequency. An internal blanking circuit prevents MOSFET switching current spike propagation and premature termination of duty cycle by internally shunting the IS input for 150 ns after the beginning of the new switching period. TI recommends an external low-pass RC filter with resistor values ranging from 100 Ω to 500 Ω for additional noise suppression when operating in the dropout region (VIN less than 7 V).
Cycle-by-cycle current limit is accomplished by a redundant internal comparator, which immediately terminates the GATE output when the IS input voltage, VIS, exceeds 525-mV (typ) threshold. Upon a current limit event, the SS and COMP pin are internally grounded to reset the state of the controller. The GATE output is enabled after the expiration of the 35-µs internal fault timer and a new start-up sequence is initiated through the SS pin.
The voltage across the LED current sense resistor, V(CSP–CSN), is regulated to the analog adjust input voltage, VIADJ, scaled by the current sense amplifier voltage gain of 14. The LED current can be linearly adjusted by varying the voltage on IADJ from 140 mV to 2.25 V using either a resistor divider from VCC or a voltage source. The IADJ pin can be connected to VCC through an external resistor to set LED current based on the 2.42-V internal reference voltage. Figure 21 shows different methods to set the IADJ voltage. The IADJ input can be used in conjunction with a NTC resistor to implement thermal foldback protection as shown in Figure 21(b). A PWM signal in conjunction with first- or second-order low-pass filter can be used to program the IADJ voltage as shown in Figure 21(c).
The TPS92691/-Q1 incorporates a dimming input (PWM) for pulse-width modulating the output LED current. The brightness of the LEDs can be linearly varied by modulating the duty cycle of the pulsating voltage source connected to the PWM input pin. Driving the PWM input below 2.3 V (typ) turns off switching, parks the oscillator, disconnects the COMP pin, and sets the DDRV output to GND in order to maintain the charge on the compensation network and output capacitors. On the rising edge of the PWM input voltage (VPWM > 2.5 V), the GATE and DDRV outputs are enabled to ramp the inductor current to the previous steady-state value. The COMP pin is connected and the error amplifier and oscillator are enabled only when the switch current sense voltage VIS exceeds the COMP voltage, VCOMP, thus immediately forcing the converter into steady-state operation with minimum LED current overshoot. The PWM pin should be connected to the VCC if dimming is not required. An internal pulldown resistor sets the input to logic-low and disables the part when the pin is disconnected or left floating.
The DDRV output follows the PWM input signal and is capable of sinking and sourcing up to 500 mA of peak current to control a low-side series connected N-channel dimming FET. Alternatively, the DDRV output can be translated with an external level-shift circuit to drive a high-side series P-channel dimming FET as shown in Figure 22. The series dimming FET is required to achieve high contrast ratio as it ensures fast rise and fall times of the LED current in response to the PWM input. Without any dimming FET, the rise and fall times are limited by the inductor slew rate and the closed-loop bandwidth of the system. Leave the DDRV pin unconnected if not used.
The soft-start feature helps the regulator gradually reach the steady-state operating point, thus reducing startup stresses and surges. The TPS92691/-Q1 clamps the COMP pin to the SS pin, separated by a diode, until LED current nears the regulation threshold. The internal 10-µA soft-start current source gradually increases the voltage on an external soft-start capacitor CSS connected to the SS pin. This results in a gradual rise of the COMP voltage from GND.
The internal 10-µA current source turns on when VCC exceeds the UVLO threshold. At the beginning of the soft-start sequence, the SS pulldown switch is active and is released when the voltage VSS drops below 25 mV. The SS pin can also be pulled down by an external switch to stop switching. When the SS pin is externally driven to enable switching, the slew-rate on the COMP pin should be controlled by choosing a compensation capacitor that avoids large startup transients. The value of CSS should be large enough to charge the output capacitor during the soft-start transition period.
The IMON pin voltage represents the LED current measured by the rail-to-rail current sense amplifier across the external current shunt resistor. The linear relationship between the IMON voltage and LED current includes the amplifier gain-factor of 14 (see Figure 14). The IMON output can be connected to an external microcontroller or comparator to facilitate LED open, short, or cable harness fault detection and mitigation based on programmable threshold VOCTH. The IMON voltage is internally clamped to 3.7 V.
The TPS92691/-Q1 device includes a dedicated OVP pin which can be used for either input or output overvoltage protection. This pin features a precision 1.24 V (typ) threshold with 20-µA (typ) of hysteresis current. The overvoltage threshold limit is set by a resistor divider network from the input or output terminal to GND. When the OVP pin voltage exceeds the reference threshold, the GATE and DDRV pins are immediately pulled low and the SS and COMP capacitors are discharged. The GATE is enabled and a new startup sequence is initiated after the voltage drops below the hysteresis threshold set by the 20-µA source current and the external resistor divider.
Internal thermal shutdown circuitry is implemented to protect the controller in the event the maximum junction temperature is exceeded. When activated, typically at 175°C, the controller is forced into a shutdown mode, disabling the internal regulator. This feature is designed to prevent overheating and damage to the device.
This device has no additional functional modes.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS92691/-Q1 controller is suitable for implementing step-up or step-down LED driver topologies including Buck, Boost, Buck-Boost, SEPIC, Cuk, and Flyback. Use the following design procedure to select component values for the TPS92691/-Q1 device. This section presents a simplified discussion of the design process for the Buck, Boost, and Buck-Boost converter. The expressions derived for Buck-Boost can also be altered to select components for a 1:1 coupled-inductor SEPIC converter. The design procedure can be easily adapted for Flyback and Cuk converter topologies.
The switch duty cycle, D, defines the converter operation and is a function of the input and output voltages. In steady state, the duty cycle is derived using expression:
Buck:
Boost:
Buck-Boost:
The minimum duty cycle, DMIN, and maximum duty cycle, DMAX, are calculated by substituting maximum input voltage, VIN(MAX), and the minimum input voltage, VIN(MIN), respectively in the previous expressions. The minimum duty cycle achievable by the device is determined by the leading edge blanking period and the switching frequency. The maximum duty cycle is limited by the internal oscillator to 93% (typ) to allow for minimum off-time. It is necessary for the operating duty cycle to be within the operating limits of the device to ensure closed-loop LED current regulation over the specified input and output voltage range.
The inductor peak-to-peak ripple current, ΔiL-PP, is typically set between 10% and 80% of the maximum inductor current, IL, as a good compromise between core loss and copper loss of the inductor. Higher ripple inductor current allows a smaller inductor size, but places more of a burden on the output capacitor to smooth the LED current ripple. Knowing the desired ripple ratio RR, switching frequency ƒSW, maximum duty cycle DMAX, and the typical LED current ILED, the inductor value can be calculated as follows:
Buck:
Boost and Buck-Boost:
As an alternative, the inductor can be selected based on CCM-DCM boundary condition specified based on output power, PO(BDRY). The choice of inductor ensures CCM operation in battery-powered LED driver applications that are designed to support different LED string configurations with a wide range of programmable LED current setpoints. The output power should be calculated based on the lowest LED current and the lowest output voltage requirements for a given application.
Buck:
Boost:
Buck-Boost:
The saturation current rating of the inductor should be greater than the peak inductor current, IL(PK), at the maximum operating temperature.
The output capacitors are required to attenuate the discontinuous or large ripple current generated by switching and achieve the desired peak-to-peak LED current ripple, ΔiLED(PP). The capacitor value depends on the total series resistance of the LED string, rD, the switching frequency, ƒSW, and on the converter topology (that is, step-up or step-down). For the Buck and Cuk topology, the inductor is in series with LED load and requires a smaller capacitor than the Boost, Buck-Boost, and SEPIC topologies to achieve the same LED ripple current. The capacitance required for the target LED ripple current can be calculated based on following equations.
Buck:
Boost and Buck-Boost:
When choosing the output capacitors, it is important to consider the ESR and the ESL characteristics as they directly impact the LED current ripple. Ceramic capacitors are the best choice due to their low ESR, high ripple current rating, long lifetime, and good temperature performance. When selecting ceramic capacitors, it is important to consider the derating factors associated with higher temperature and DC bias operating conditions. TI recommends an X7R dielectric with voltage rating greater than maximum LED stack voltage. An aluminum electrolytic capacitor can be used in parallel with ceramic capacitors to provide bulk energy storage. The aluminum capacitors must have necessary RMS current and temperature ratings to ensure prolonged operating lifetime. The minimum allowable RMS output capacitor current rating, ICOUT(RMS), can be approximated:
Buck:
Boost and Buck-Boost:
The expressions (Equation 14 to Equation 17) are best suited for designs driving a fixed LED load, with known output voltage and LED current. For applications that are required to support different LED string configurations with a wide range of programmable LED current setpoints, the previous expressions are rearranged to reflect output capacitance based on the maximum output power, PO(MAX), to ensure that LED current ripple specifications are met over the entire range of operation. Typical Buck-Boost LED Driver provides the details for Buck-Boost LED driver.
The input capacitors, CIN, smooth the input voltage ripple and store energy to supply input current during input voltage or PWM dimming transients. The series inductor in the Boost, SEPIC, and Cuk topology provides continuous input current and requires a smaller input capacitor to achieve desired input ripple voltage, ΔvIN(PP). The Buck and Buck-Boost topology have discontinuous input current and require a larger capacitor to achieve the same input voltage ripple. Based on the switching frequency, ƒSW, and the maximum duty cycle, DMAX, the input capacitor value can be calculated as follows:
Buck:
Boost:
Buck-Boost:
X7R dielectric-based ceramic capacitors are the best choice due to their low ESR, high ripple current rating, and good temperature performance. For applications using PWM dimming, TI recommends an aluminum electrolytic capacitor in addition to ceramic capacitors to minimize the voltage deviation due to large input current transients generated in conjunction with the rising and falling edges of the LED current.
For most applications, TI highly recommends to bypass the VIN pin with a 0.1-µF ceramic capacitor placed as close as possible to the device and add a series 10-Ω resistor to create a 150-kHz low-pass filter and eliminate undesired high-frequency noise.
The power MOSFET should be able to sustain the maximum switch node voltage, VSW, and switch RMS current derived based on the converter topology. TI recommends a drain voltage VDS rating of at least 20% greater than the maximum switch node voltage to ensure safe operation. The MOSFET drain-to-source breakdown voltage, VDS, and RMS current ratings are calculated using the following expressions.
Buck:
Boost:
Buck-Boost:
Where the voltage, VO(OV), is the overvoltage protection threshold and the worst-case output voltage under fault conditions.
Select a MOSFET with low total gate charge, Qg, to minimize gate drive and switching losses. The MOSFET RDS resistance is usually a less critical parameter because the switch conduction losses are not a significant part of the total converter losses at high operating frequencies. The switching and conduction losses are calculated as follows:
CRSS is the MOSFET reverse transfer capacitance. IL is the average inductor current. IGATE is gate drive output current, typically 500 mA. The MOSFET power rating and package should be selected based on the total calculated loss, the ambient operating temperature, and maximum allowable temperature rise.
A Schottky diode (when used as a rectifier) provides the best efficiency due to low forward voltage drop and near-zero reverse recovery time. TI recommends a diode with a reverse breakdown voltage, VD(BR), greater than or equal to MOSFET drain-to-source voltage, VDS, for reliable performance. It is important to understand the leakage current characteristics of the Schottky diode, especially at high operating temperatures because it impacts the overall converter operation and efficiency.
The current through the diode, ID, is given by:
The diode should be sized to exceed the current rating, and the package should be able to dissipate power without exceeding the maximum allowable temperature.
The LED current is set by the external current sense resistor, RCS, and the analog adjust voltage, VIADJ. The current sense resistor is placed in series with the LED load and can be located either on the high side (connected to the output, VO), or on the low side (connected to ground, GND). The CSP and CSN inputs of the internal rail-to-rail current sense amplifier are connected to the RCS resistor to enable closed-loop regulation. When VIADJ > 2.5 V, the internal 2.42-V reference sets the V(CSP-CSN) threshold to 172 mV and the LED current is regulated to:
The LED current can be programmed by varying VIADJ between 140 mV to 2.25 V. The LED current can be calculated using:
The output voltage ripple should be limited to 50 mV for best performance. TI recommends a low-pass common-mode filter consisting of 10-Ω resistors is series with CSP and CSN inputs and 0.01-µF capacitors to ground to minimize the impact of voltage ripple and noise on LED current accuracy (see Figure 20). A 0.1-µF capacitor across CSP and CSN is included to filter high-frequency differential noise.
The switch current sense resistor, RIS, is used to implement peak current mode control and to set the peak switch current limit. The value of switch current sense RIS is selected to achieve stable inner current loop operation based on the magnitude of slope compensation ramp, VSL, and to protect the main switching MOSFET under fault conditions. The lower of the two values calculated using the following equations should be selected for RIS.
The internal slope compensation voltage, VSL is fixed at 200 mV (typ). A resistor can be placed in series with the IS pin to increase slope compensation, if necessary. The peak switch current limit is set based on the internal current limit threshold of 525 mV (typ) and adjusted based on slope compensation to ensure reliable operation while PWM dimming.
The use of a 1-nF and 100-Ω low-pass filter is optional. If used, the resistor value should be less than 500 Ω to limit its influence on the internal slope compensation signal.
The open-loop response is the product of the modulator transfer function (shown in Equation 34) and the feedback transfer function. Using a first-order approximation, the modulator transfer function can be modeled as a single pole created by the output capacitor, and in the boost and buck-boost topologies, a right half-plane zero created by the inductor, where both have a dependence on the LED string dynamic resistance, rD. Because TI recommends a ceramic capacitor, the ESR of the output capacitor is neglected in the analysis. The small-signal modulator model also includes a DC gain factor that is dependent on the duty cycle, output voltage, and LED current.
Table 1 summarizes the expression for the small-signal model parameters.
The feedback transfer function includes the current sense resistor and the loop compensation of the transconductance amplifier. A compensation network at the output of the error amplifier is used to configure loop gain and phase characteristics. A simple capacitor, CCOMP, from COMP to GND (as shown in Figure 30) provides integral compensation and creates a pole at the origin. Alternatively, a network of RCOMP, CCOMP, and CHF, shown in Figure 31, can be used to implement proportional and integral (PI) compensation and to create a pole at the origin, a low-frequency zero, and a high-frequency pole.
DC GAIN (G0) | POLE FREQUENCY (ωP) | ZERO FREQUENCY (ωZ) | |
---|---|---|---|
Buck | 1 | ![]() |
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Boost | ![]() |
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Buck-Boost | ![]() |
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The feedback transfer function is defined as follows.
Feedback transfer function with integral compensation:
Feedback transfer function with proportional integral compensation:
The pole at the origin minimizes output steady-state error. High bandwidth is achieved with the PI compensator by placing the low-frequency zero an order of magnitude less than the crossover frequency. Use the following expressions to calculate the compensation network.
Buck with integral compensator:
Boost and Buck-Boost with proportional integral compensator:
The loop response is verified by applying step input voltage transients. The goal is to minimize LED current overshoot and undershoot with a damped response. Additional tuning of the compensation network may be necessary to optimize PWM dimming performance.
The soft-start time (tSS) is the time required for the LED current to reach the target setpoint. The required soft-start time, tSS, is programmed using a capacitor, CSS, from SS pin to GND, and is based on the LED current, output capacitor, and output voltage.
The overvoltage threshold is programmed using a resistor divider, ROV2 and ROV1, from the output voltage, VO, to ground for Boost and SEPIC topologies, as shown in Figure 24 and Figure 25. If the LEDs are referenced to a potential other than ground, as in the Buck-Boost or Buck configuration, the output voltage is sensed and translated to ground by using a PNP transistor and level-shift resistors, as shown in Figure 27 and Figure 26. The overvoltage turn-off threshold, VO(OV), is:
Boost:
Buck and Buck-Boost:
The overvoltage hysteresis, VOV(HYS) is:
When PWM dimming, the TPS92691/-Q1 requires another MOSFET placed in series with the LED load. This MOSFET should have a voltage rating greater than the output voltage, VO, and a current rating at least 10% higher than the nominal LED current, ILED.
It is important to control the slew-rate of the external FET to achieve a damped LED current response to PWM rising-edge transitions. For a low-side, N-channel dimming FET, the slew-rate is controlled by placing a resistor in series with the GATE pin. The rise and fall times depend on the value of the resistor and the gate-to-source capacitance of the MOSFET. The series resistor can be bypassed with a diode for fast rise time and slow fall times to achieve 100:1 or higher contrast ratios. If a high-side P-channel dimming FET is used, the rise and fall times can be controlled by selecting appropriate resistors for the level-shift network, RLS1 and RLS2, as shown in Figure 26.
Figure 32. Boost LED Driver With High-Side Current Sense
Table 2 shows the design parameters for the boost LED driver application.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT CHARACTERISTICS | ||||||
Input voltage range | 7 | 14 | 18 | V | ||
Input UVLO setting | 4.5 | V | ||||
OUTPUT CHARACTERISTICS | ||||||
LED forward voltage | 3.2 | V | ||||
Number of LEDs in series | 12 | |||||
VO | Output voltage | LED+ to LED– | 38.4 | V | ||
ILED | Output current | 500 | mA | |||
RR | LED current ripple ratio | 5% | ||||
rD | LED string resistance | 4 | Ω | |||
Maximum output power | 20 | 25 | W | |||
PWM dimming range | 240-Hz PWM frequency | 4% | 100% | |||
SYSTEMS CHARACTERISTICS | ||||||
ΔiL(PP) | Inductor current ripple | 20% | ||||
ΔvIN(PP) | Input voltage ripple | 70 | mV | |||
VO(OV) | Output overvoltage protection threshold | 50 | V | |||
VOV(HYS) | Output overvoltage protection hysteresis | 5 | V | |||
tss | Soft-start period | 8 | ms | |||
Switching frequency | 390 | kHz |
This procedure is for the boost LED driver application.
Solve for D, DMAX, and DMIN:
Solve for RT:
The closest standard resistor of 20 kΩ is selected.
The inductor value should ensure continuous conduction mode (CCM) of operation and should achieve desired ripple specification, ΔiL(PP).
Solving for inductor:
The closest standard inductor is 27 µH. The expected inductor ripple based on the chosen inductor is:
The inductor saturation current rating should be greater than the peak inductor current, IL(PK).
The specified peak-to-peak LED current ripple, ΔiLED(PP), is:
The output capacitance required to achieve the target LED current ripple is:
Considering 40% derating factor under DC bias operation, four 4.7-µF, 100-V rated X7R ceramic capacitors are used in parallel to achieve a combined output capacitance of 18.8 µF.
The input capacitor is required to reduce switching noise conducted through the input wires and reduced the input impedance of the LED driver. The capacitor required to limit peak-to-peak input ripple voltage ripple, ΔvIN(PP), to 70 mV is given by:
A 4.7-µF, 50-V X7R ceramic capacitor is selected.
The MOSFET ratings should exceed the maximum output voltage and RMS switch current given by:
A 60-V or a 100-V N-channel MOSFET with current rating exceeding 3 A is required for this design.
The diode should be selected based on the following voltage and current ratings:
A 60-V or a 100-V Schottky diode with low reverse leakage current is suitable for this design. The package must be able to handle the power dissipation resulting from continuous forward current, ID, of 0.5 A.
LED current is based on the current shunt resistor, RCS and the V(CSP-CSN) threshold set by the voltage on the IADJ pin VIADJ. By default, IADJ is tied to VCC via an external resistor to enable the internal reference voltage of 2.42 V that then sets the V(CSP-CSN) threshold to 172 mV. The current shunt resistor value is calculated by:
Two 0.68-Ω resistors are connected in parallel to achieve RCS of 0.34 Ω.
The switch current sense resistor, RIS, is calculated by solving the following equations and choosing the lowest value:
A standard value of 0.1 Ω is selected.
The modulator transfer function for the Boost converter is derived for nominal VIN voltage and corresponding duty cycle, D, and is given by the following equation. (See Table 1 for more information.)
The proportional-integral compensator components CCOMP and RCOMP are obtained by solving the following expressions:
The closet standard capacitor of 33 nF and resistor of 2.15 kΩ is selected. The high frequency pole location is set by a 100 pF CHF capacitor.
The soft-start capacitor required to achieve start-up in 8 ms is given by:
The closet standard capacitor of 100 nF is selected.
The overvoltage protection threshold of 50 V and hysteresis of 5 V is set by the ROV1 and ROV2 resistor divider.
The standard resistor values of 249 kΩ and 6.34 kΩ are chosen.
A series dimming FET is required to meet PWM dimming specification from 100% to 4% duty cycle. A 60-V, 2-A N-channel FET is suitable for this application.
As an alternative, a 60-V, 2-A P-channel FET could be used to achieve PWM dimming. An external level-shift circuit is required to translate the DDRV signal to the gate of the P-channel dimming FET. The drive strength of 5 mA and gate-source voltage of 15 V are set by the 1-kΩ and 2-kΩ level-translator resistors and a small-signal N-channel MOSFET, whose gate is connected to DDRV.
By default, the PWM pin is connected to VCC through a 100-kΩ resistor to enable the part upon start-up.
These curves are for the boost LED driver.
Figure 41. Buck-Boost LED Driver
Buck-Boost LED drivers provide the flexibility needed in applications that support multiple LED load configurations. For such applications, it is necessary to modify the design procedure presented in Application Information to account for the wider range of output voltage and LED current specifications. This design is based on the maximum output power PO(MAX), set by the lumen output specified for the lighting application. The design procedure for a battery connected application with 3 to 9 LEDs in series and maximum 15 W output power is outlined in this section.
For applications that have a fixed number of LEDs and a narrow LED current range (for brightness correction), design equations provided in the Application Information and simplified design procedure, similar to one outlined in Typical Boost LED Driver for Boost LED driver, are recommended for developing an optimized circuit with lower Bill of Material (BOM) cost.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT CHARACTERISTICS | ||||||
Input voltage range | 7 | 14 | 18 | V | ||
Input UVLO setting | 4.5 | V | ||||
OUTPUT CHARACTERISTICS | ||||||
LED forward voltage | 3.2 | V | ||||
Number of LEDs in series | 3 | 6 | 9 | |||
VO | Output voltage | LED+ to LED– | 9.6 | 19.2 | 28.8 | V |
ILED | Output current | 500 | 750 | 1500 | mA | |
ΔiLED(PP) | LED current ripple | 5% | ||||
rD | LED string resistance | 1 | 2 | 3 | Ω | |
PO(MAX) | Maximum output power | 15 | W | |||
PWM dimming range | 240-Hz PWM frequency | 4% | 100% | |||
SYSTEMS CHARACTERISTICS | ||||||
PO(BDRY) | Output power at CCM-DCM boundary condition | 5 | W | |||
ΔvIN(PP) | Input voltage ripple | 70 | mV | |||
VO(OV) | Output overvoltage protection threshold | 40 | V | |||
VOV(HYS) | Output overvoltage protection hysteresis | 5 | V | |||
tss | Soft-start period | 8 | ms | |||
Switching frequency | 390 | kHz |
Solving for D, DMAX, and DMIN:
Solving for RT resistor:
The inductor is selected to meet the CCM-DCM boundary power requirement, PO(BDRY). Typically, the boundary condition is set to enable CCM operation at the lowest possible operating power based on minimum LED forward voltage drop and LED current. In most applications, PO(BDRY) is set to be 1/3 of the maximum output power, PO(MAX). The inductor value is calculated for maximum input voltage, VIN(MAX), and output voltage, VO(MAX):
The closest standard value of 33 µH is selected. The inductor ripple current is given by:
The inductor saturation rating should exceed the calculated peak current which is based on the maximum output power using the following expression:
The output capacitor should be selected to achieve the 5% peak-to-peak LED current ripple specification. Based on the maximum power, the capacitor is calculated as follows:
A minimum of four 10-µF, 50-V X7R ceramic capacitors in parallel are needed to meet the LED current ripple specification over the entire range of output power. Additional capacitance may be required based on the derating factor under DC bias operation.
The input capacitor is calculated based on the peak-to-peak input ripple specifications, ΔvIN(PP). The capacitor required to limit the ripple to 70 mV over range of operation is calculated using:
A parallel combination of four 10-µF, 50-V X7R ceramic capacitors are used for a combined capacitance of 40 µF. Additional capacitance may be required based on the derating factor under DC bias operation.
Calculating the minimum transistor voltage and current rating:
This application requires a 60-V or 100-V N-channel MOSFET with a current rating exceeding 3 A.
Calculating the minimum Schottky diode voltage and current rating:
This application requires a 60-V or 100-V Schottky diode with a current rating exceeding 1.5 A. TI recommends a single high-current diode instead of paralleling multiple lower-current-rated diodes to ensure reliable operation over temperature.
Solving for RIS:
A standard resistor of 0.1 Ω is selected based on the lower of the two calculated values. The resistor ensures stable current loop operation with no subharmonic oscillations over the entire input and output voltage ranges.
The LED current can be programmed to match the LED string configuration by using a resistor divider, RADJ1 and RADJ2, from VCC to GND for a given sense resistor, RCS, as shown in Figure 21. To maximize the accuracy, the IADJ pin voltage is set to 2.1 V for the specified LED current of 1.5 A. The current sense resistor, RCS, is then calculated as:
A standard resistor of 0.1 Ω is selected. Table 4 summarizes the IADJ pin voltage and the choice of the RADJ1 and RADJ2 resistors for different current settings.
LED CURRENT | IADJ VOLTAGE (VIADJ) | RADJ1 | RADJ2 |
---|---|---|---|
500 mA | 700 mV | 10.2 kΩ | 100 kΩ |
750 mA | 1.05 V | 16.2 kΩ | 100 kΩ |
1.5 A | 2.1 V | 39.2 kΩ | 100 kΩ |
A simple integral compensator provides a good starting point to achieve stable operation across the wide operating range. The modulator transfer function with the lowest frequency pole location is calculated based on maximum output voltage, VO(MAX), duty cycle, DMAX, LED dynamic resistance, rD(MAX), and minimum LED string current, ILED(MIN). (See Table 1 for more information.)
The compensation capacitor needed to achieve stable response is:
A 100 nF capacitor is selected.
A proportional integral compensator can be used to achieve higher bandwidth and improved transient performance. However, it is necessary to experimentally tune the compensator parameters over the entire operating range to ensure stable operation.
Solving for soft-start capacitor, CSS, based on 8-ms startup duration:
A 100-nF soft-start capacitor is selected.
Solving for resistors, ROV1 and ROV2:
The closest standard values of 249 kΩ and 7.87 kΩ along with a 60-V PNP transistor are used to set the OVP threshold to 40 V with 5 V of hysteresis.
A 60-V, 2-A P-channel FET is used in conjunction with an external level-shift circuit to achieve PWM dimming. The drive strength of 5 mA and gate-source voltage of 15 V are set by the 1-kΩ and 2-kΩ level-translator resistors and a small-signal N-channel MOSFET, whose gate is connected to DDRV.
These curves are for the buck-boost LED driver.
VIN = 14 V |
VIN = 14 V |