The TPSI2140-Q1 is an isolated solid state relay designed for high voltage automotive and industrial applications. The TPSI2140-Q1 uses TI's high reliability capacitive isolation technology in combination with internal back-to-back MOSFETs to form a completely integrated solution requiring no secondary side power supply.
The primary side of the device is powered by only 9 mA of input current and incorporates a fail-safe EN pin preventing any possibility of back powering the VDD supply. In most applications, the VDD pin of the device should be connected to a system supply between 5 V–20 V and the EN pin of the device should be driven by a GPIO output with logic HI between 2.1 V–20 V. In other applications, The VDD and EN pins could be driven together directly from the system supply or from a GPIO output. All control configurations of the TPSI2140-Q1 do not require additional external components such as a resistor and/or low side switch that are typically required in photo relay solutions.
The secondary side consists of back-to-back MOSFETs with a standoff voltage of ±1.2 kV from S1 to S2. The TPSI2140-Q1 MOSFET's avalanche robustness and thermally conscious package design allow it to robustly support system level dielectric withstand testing (HiPot) and DC fast charger surge currents of up to 2 mA without requiring any external components.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
TPSI2140-Q1 | SOIC 11-pin (DWQ) | 10.3 mm × 7.5 mm |
Changes from Revision A (November 2022) to Revision B (June 2023)
PIN NO. | PIN NAME | TYPE(1) | DESCRIPTION |
---|---|---|---|
1 | VDD | P | Power supply for primary side |
2 | GND | GND | Ground supply for primary side |
3 | EN | I | Active high switch enable signal |
4 | NC/GND | NC/GND | Internally connected, connect externally to ground or leave floating |
5 | NC/GND | NC/GND | Internally connected, connect externally to ground or leave floating |
6 | NC/GND | NC/GND | Internally connected, connect externally to ground or leave floating |
7 | NC/GND | NC/GND | Internally connected, connect externally to ground or leave floating |
8 | GND | GND | Internally connected to GND, connect externally to ground or leave floating |
9 | S2 | I/O | Switch input |
10 | SM | NC | For thermal dissipation only, see Layout Guidelines for more information |
11 | S1 | I/O | Switch input |
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
VVDD | Primary side supply voltage(2) | –0.3 | 20.7 | V |
VEN | Enable voltage(2) | –0.3 | 20.7 | V |
IS1,S2 | Switch current, S1/S2 | –55 | 55 | mA |
IAVA,S1,S2 | Repetitive avalanche rating, 5s pulse, S1/S2(3) | –2 | 2 | mA |
Repetitive avalanche rating, 60s pulse, S1/S2(4) | –1 | 1 | mA | |
TJ | Junction temperature | –40 | 150 | °C |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
HBMPrim | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) HBM ESD Classification Level 2 | Primary Side Pins No. 1-8 | ±2000 | V |
HBMSec | Human body model (HBM), per AEC Q100-002(1) HBM ESD Classification Level 1C | Secondary Side Pins No. 9-11 | ±1500 | V | |
CDM | Electrostatic discharge | Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4 |
All pins | ±750 | V |
PARAMETER | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|
VVDD | Primary side supply voltage(1) | 4.5 | 20 | V | |
VEN | Enable voltage(1) | 0 | 20 | V | |
VS2-S1 | Switch input voltage | –1200 | 1200 | V | |
IS1,S2 | Switch current | –50 | 50 | mA | |
TA | Ambient operating temperature | –40 | 125 | °C | |
TJ | Junction operating temperature | –40 | 150 | °C |
THERMAL METRIC (1) | DEVICE | UNIT | |
---|---|---|---|
DWQ (SOIC) | |||
11 PINS | |||
RϴJA | Junction-to-ambient thermal resistance | 70 | °C/W |
RϴJA, EVM, 60S | Junction-to-ambient thermal resistance(2)(3) | 52 | °C/W |
RϴJA, EVM, 5S | Junction-to-ambient thermal resistance(2)(4) | 30 | °C/W |
RϴJB | Junction-to-board thermal resistance | 22 | °C/W |
RϴJC(top) | Junction-to-case (top) thermal resistance | 26 | °C/W |
ψJT | Junction-to-top characterization parameter | 14 | °C/W |
ΨJB | Junction-to-board characterization parameter | 21 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PD | Maximum power dissipation, total | VVDD = 5 V, VEN = 5 V peak to peak, VS1-S2 = 1200V, RS1 = 500kΩ fEN = 1Hz square wave |
31 | mW | ||
PD_P | Maximum power dissipation (primary) | 30 | mW | |||
PD_S | Maximum power dissipation (secondary) | 1 | mW |
PARAMETER | TEST CONDITIONS | VALUE | UNIT | |
---|---|---|---|---|
IEC 60664-1 | ||||
CLR | External clearance(1) | Shortest terminal-to-terminal distance through air | >8 | mm |
CPG | External Creepage(1) | Shortest terminal-to-terminal distance across the package surface | >8 | mm |
DTI | Distance through the insulation | Minimum internal gap (internal clearance) | >10.5 | µm |
CTI | Comparative tracking index | DIN EN 60112 (VDE 0303-11); IEC 60112 | >600 | V |
Material Group | According to IEC 60664-1 | I | ||
Overvoltage category per IEC 60664-1 | Rated mains voltage ≤ 300 VRMS | I-IV | ||
Rated mains voltage ≤ 600 VRMS | I-III | |||
Rated mains voltage ≤ 1000 VRMS | I-II | |||
DIN V VDE 0884-11:2017-01(2), IEC 60747-17:2020 | ||||
VIORM | Maximum repetitive peak isolation voltage | AC voltage (bipolar) | 1414 | VPK |
VIOWM | Maximum isolation working voltage | AC voltage (sine wave) | 1000 | VRMS |
DC voltage | 1500 | VDC | ||
VIOTM | Maximum transient isolation voltage | VTEST = VIOTM, t = 60 s (qualification) | 5300 | VPK |
VTEST = 1.2 × VIOTM, t = 1 s (100% production) | 6360 | VPK | ||
VIOSM | Maximum surge isolation voltage(3) | Tested in oil per IEC 62638-1, 1.2/50 µs waveform, VTEST = 1.3 × VIOSM = 6500 VPK (qualification) | 5000 | VPK |
qpd | Apparent charge(4) | Method a: After I/O safety test subgroup 2/3,Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 1800 VPK, tm = 10 s | ≤5 | pC |
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.3 × VIORM = 1950 VPK, tm = 10 s | ≤5 | |||
Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s; Vpd(m) = 1.5 × VIORM = 2250 VPK, tm = 1 s | ≤5 | |||
CIO | Barrier capacitance, input to output(5) | VIO = 0.4 × sin (2πft), f = 1 MHz | 4 | pF |
RIO | Insulation resistance, input to output(5) | VIO = 500 V, TA = 25°C | >1012 | Ω |
VIO = 500 V, 100°C ≤ TA ≤ 125°C | >1011 | |||
VIO = 500 V at TS = 150°C | >109 | |||
Pollution degree | 2 | |||
Climatic category | 40/150/21 | |||
UL 1577 | ||||
VISO | Withstand isolation voltage | VTEST = VISO, t = 60 s (qualification) VTEST = 1.2 × VISO, t = 1 s (100% production) |
3750 | VRMS |
Misc. | ||||
VISO | Withstand isolation voltage | 5300 | VDC |
VDE | CSA | UL | CQC | TUV |
---|---|---|---|---|
Plan to certify according to DIN V VDE V 0884-11:2017-01 | Not Planned, contact TI to request. |
Plan to certify according to UL 1577 Component Recognition Program | Not Planned, contact TI to request. |
Not Planned, contact TI to request. |
Maximum transient isolation voltage, 5300 VPK; Maximum repetitive peak isolation voltage, 1500 VPK; Maximum surge isolation voltage, 6000 VPK |
Single protection, 3750 VRMS | |||
Certificate planned | Certificate planned |
PARAMETER(1)(2) | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
IS | Safety VDD Current | RθJA = 70°C/W, VVDD = 20 V, TJ = 150°C, TA = 25°C |
77 | mA | ||
Safety Switch Current (On State) | RθJA = 70°C/W, VVDD = 20 V, TJ = 150°C, TA = 25°C |
71 | ||||
Safety Switch Current (Off State, 5 second) | RθJA, EVM, 5S(3) = 30°C/W, VVDD = 0 V, TJ = 150°C, TA = 25°C |
2.7 | ||||
Safety Switch Current (Off State, 60 second) | RθJA, EVM, 60S(3) = 52°C/W, VVDD = 0 V, TJ = 150°C, TA = 25°C |
1.5 | ||||
PS | Safety input, output, or total power | RθJA = 70°C/W, TJ = 150°C, TA = 25°C. |
1.78 | W | ||
TS | Maximum safety temperature | 150 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PRIMARY SIDE SUPPLY (VDD) | ||||||
VUVLO_R | VDD undervoltage threshold rising | VDD rising | 4 | 4.2 | 4.4 | V |
VUVLO_F | VDD undervoltage threshold falling | VDD falling | 3.9 | 4.1 | 4.3 | V |
VUVLO_HYS | VDD undervoltage threshold hysteresis | 40 | 100 | 150 | mV | |
IVDD_ON | VDD current, device powered on | TJ = 25°C | 9 | 11 | mA | |
VDD current, device powered on | –40°C ≤ TJ ≤ 150°C | 9 | 12 | mA | ||
IVDD_OFF | VDD current, 5 V, device powered off | VVDD = 5 V, VEN = 0 V, TJ = 25°C | 3.5 | 8 | µA | |
VVDD = 5 V, VEN = 0 V, TJ = 105°C | 4.5 | 11 | µA | |||
VVDD = 5 V, VEN = 0 V, TJ = 125°C | 5.2 | 16 | µA | |||
VVDD = 5 V, VEN = 0 V, –40°C ≤ TJ ≤ 150°C | 30 | µA | ||||
VDD current, 20 V, device powered off | VVDD = 20 V, VEN = 0 V, TJ = 25°C | 8 | 10.5 | µA | ||
VVDD = 20 V, VEN = 0 V, TJ = 105°C | 10 | 17 | ||||
VVDD = 20 V, VEN = 0 V, TJ = 125°C | 11 | 25 | ||||
VVDD = 20 V, VEN = 0 V, –40°C ≤ TJ ≤ 150°C | 40 | |||||
FET CHARACTERISTICS (S1, S2) | ||||||
RDSON | On resistance | IO = 2 mA, TJ = 25°C | 130 | 175 | Ω | |
IO = 2 mA, TJ = 85°C | 176 | 235 | ||||
IO = 2 mA, TJ = 105°C | 192 | 250 | ||||
IO = 2 mA, TJ = 125°C | 210 | 275 | ||||
IO = 2 mA, –40°C ≤ TJ ≤ 150°C | 300 | |||||
IOFF | Off leakage, 1200 V | V = +/–1200 V, TJ = 25°C | 0.02 | 0.1 | µA | |
V = +/–1200 V, TJ = 85°C | 0.5 | |||||
V = +/–1200 V, TJ = 105°C | 1.5 | |||||
V = +/–1200 V, TJ = 125°C | 6 | |||||
V = +/–1200 V, –40°C ≤ TJ ≤ 150°C | 50 | |||||
Off leakage, 1000 V | V = +/–1000 V, TJ = 25°C | 0.02 | 0.1 | µA | ||
V = +/–1000 V, TJ = 85°C | 0.3 | |||||
V = +/–1000 V, TJ = 105°C | 1 | |||||
V = +/–1000 V, TJ = 125°C | 4 | |||||
V = +/–1000 V, –40°C ≤ TJ ≤ 150°C | 35 | |||||
VAVA | Avalanche voltage | IO = 10 µA, TJ = 25°C | 1300 | 1550 | V | |
IO = 100 µA, TJ = 150°C | 1300 | 1550 | ||||
VSM_OFF | SM voltage | VS1 = 1000 V, VS2 = 0 V OR VS2 = 1000 V, VS1 = 0 V | 400 | 600 | V | |
COSS | S1, S2 capacitance | VS1,S2 = 0 V, SM float, F = 1 MHz | 75 | pF | ||
LOGIC-LEVEL INPUT (EN) | ||||||
VIL | Input logic low voltage | 0.0 | 0.8 | V | ||
VIH | Input logic high voltage | 2.1 | 20.0 | V | ||
VHYS | Input logic hysteresis | 100 | 250 | 300 | mV | |
IIL | Input logic low current | VEN = 0 V | –0.1 | 0.1 | µA | |
IIL | Input logic low current | VEN = 0.8 V | 2 | 4 | 6.5 | µA |
IIH | Input logic high current | VEN = 5 V | 10 | 22 | 50 | µA |
IIH | Input logic high current | VEN = 20 V | 100 | 175 | 350 | µA |
IVDD_FS | VDD fail-safe current | VEN = 20 V, VVDD = 0 V | –0.1 | 0.1 | µA | |
RPD | Pulldown resistance | Two point measurement, VEN = 0.5 V and VEN = 0.8 V | 100 | 200 | 350 | kΩ |
NOISE IMMUNITY | ||||||
CMTI | Common-mode transient immunity | |VCM| = 1000 V | 100.0 | V/ns |
MODE | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
Switching Characteristics | |||||||
EN switching | tPD_ON | Input HI to Output voltage falling propagation delay | VIN = 1000 V RL = 1 MΩ | 100 | 300 | µs | |
tF | Output fall time | 20 | 100 | ||||
tON | Input HI to Output LO delay | 160 | 400 | ||||
tPD_OFF | Input LO to Output voltage rising propagation delay | 150 | 200 | ||||
tR | Output rise time | 50 | 600 | ||||
tOFF | Input LO to Output HI delay | 200 | 700 | ||||
EN and VDD switching | tPD_ON | Input HI to Output voltage falling propagation delay | VIN = 1000 V RL = 1 MΩ | 240 | 400 | µs | |
tF | Output fall time | 20 | 100 | ||||
tON | Input HI to Output LO delay | 260 | 500 | ||||
tPD_OFF | Input LO to Output voltage rising propagation delay | 150 | 200 | ||||
tR | Output rise time | 50 | 600 | ||||
tOFF | Input LO to Output HI delay | 200 | 700 |
The TPSI2140-Q1 is an isolated solid state relay designed for high voltage automotive and industrial applications. TI's high reliability capacitive isolation technology in combination with back-to-back MOSFETs form a completely integrated solution requiring no secondary side power supply.
As seen in the Functional Block Diagram, the primary side consists of a driver which delivers power and enable logic information to each of the internal MOSFETs on the secondary side. The on-board oscillator controls the frequency of the driver's operation and the Spread Spectrum Modulation (SSM) controller varies the driver frequency to improve system EMI performance. When the enable pin is brought HI and the VDD voltage is above the UVLO threshold, the oscillator starts and the driver sends power and a logic HI across the barrier. When the enable pin is brought LO or the VDD voltage falls below the UVLO threshold, the driver is disabled. The lack of activity communicates a logic LO to the secondary side and the MOSFETs are disabled.
Each MOSFET on the secondary side has a dedicated full-bridge rectifier to form its local power supply and a receiver. The receiver determines the logic state delivered from the primary side through the capacitive isolation barrier and uses a slew rate controlled driver to drive the MOSFET's gate. Each receiver performs signal conditioning on the signals received across the barrier in order to filter common mode interference and ensure that the MOSFETs are controlled according to the logic sent by the primary side driver and the system.
The avalanche robust MOSFETs and the thermal benefits of the widened pins on the 11 DWQ package enable the TPSI2140-Q1 to support dielectric withstand testing (HiPot) and DC fast charger surge currents of up to 2 mA without requiring any external protection components.
When the voltage between the S1 and S2 pins exceeds +/-1200 V the secondary side MOSFETs could enter an avalanche mode of operation. The MOSFETs and the 11 DWQ package have been designed and qualified to be robust in this mode of operation to support Dielectric Withstand Testing (HiPot). To help ensure the thermal performance of the the system in this mode of operation, refer to the PCB Layout Guidelines.
VDD | EN | S1-S2 State | COMMENTS |
---|---|---|---|
Powered Up(1) | L | OFF | VDD current is in OFF state range. |
H | ON | VDD current is in ON state range. | |
Powered Down(2) | L | OFF | VDD current is in OFF state range. |
H | OFF | Primary side analog is powered on, VDD current is between OFF state and ON state ranges. |
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
The TPSI2140-Q1 is a 1200-V, 50-mA automotive isolated switch optimized for high voltage switching in measurement applications, especially those that require switching across an isolation barrier or galvanically isolated domain. Common end equipments include energy storage systems (ESS), solar panel arrays, EV chargers, and EV battery management systems. The device enables the system designer to reduce cost and improve reliability by replacing mechanical relays and optically isolated devices.
The TPSI2140-Q1's enable input is fail safe and does not need to be driven from the same domain as the VDD pin supply.
The TPSI2140-Q1 supports an input voltage range of 4.5 V to 20 V on the VDD primary supply pin and a logic high of 2.1 V to 20 V on the enable pin. The secondary side supports high voltage switching from –1200 V to 1200 V.
The TI reference designs linked below are a helpful introduction to high voltage applications using the TPSI2140-Q1. To maximize the thermal performance of the TPSI2140-Q1 for dielectric withstand testing (HiPot), please follow the Layout Guidelines contained within this datasheet.
In high voltage applications such as electric vehicle systems, the high voltage battery pack is intentionally isolated from the chassis domain of the car to protect the driver and prevent damage to electrical components. These systems actively monitor the integrity of this insulation to ensure the safety of the system throughout its lifetime. This active monitoring is referred to as insulation resistance monitoring (also known as isolation check, insulation check, isolation monitoring, insulation monitoring, and residual current monitoring (RCM)) and is performed by measuring the resistances from each of the battery terminals to the chassis ground, illustrated below as RISOP and RISON.
There are multiple design architectures using the TPSI2140-Q1 to measure these insulation resistances, RISOP and RISON. Some architectures employ a microcontroller that performs measurements from the high voltage domain, which will be referred to in this document as the Battery V- Reference architecture. Others use a microcontroller in the low voltage domain, which will be referred to in this document as the Chassis Ground Reference architecture. The primary difference between the two architectures is the node that the MCU uses as its GND reference. An example of a Battery V- MCU is the BQ79631-Q1 UIR sensor.
The two following sections demonstrate the measurement algorithms and the systems of equations used to calculate the isolation resistances using each architecture.
A Battery V- Reference architecture is shown below with the TPSI2140-Q1 illustrated as a switch (SW1 and SW2). SW2 initiates a connection between the chassis and PACK- and enables the measurement path to the ADC. SW1 initiates a connection between the chassis and the PACK+. RDIV1 and RDIV2 form a divider which scales the measured voltages down to the appropriate ADC range.
Two ADC measurements must be taken in order to obtain enough information to calculate the two unknown isolation resistances. The first measurement is taken with SW1 open and SW2 closed. The second measurement is taken with SW1 closed and SW2 closed. With these two measurements it is possible to solve the system of equations and calculate RISOP and RISON.
In the following example the voltage on the chassis ground is arbitrarily referred to as VRISONx.
For the first ADC measurement SW2 is closed as shown below and the following equations relate the ADC voltage to the other parameters in the system in this condition:
For the second ADC measurement SW1 and SW2 are closed as shown below and the following equations relate the ADC voltage to the other parameters in the system in this condition:
A Chassis Ground Reference architecture is shown below. SW1 and SW2 initiate connections to the PACK+ and PACK-, and enable their corresponding measurement paths to their ADCs through their corresponding resistor dividers. RDIV1, RDIV2, RDIV3, and RDIV4 scale the measured voltages down to the appropriate ADC ranges.
This first measurement is taken with SW1 closed and SW2 open and the second measurement is taken with SW1 open and SW2 closed.
The circuits in Figure 9-8 and Figure 9-9 demonstrate how to connect the TPSI2140-Q1 as a switch in each of the architectures above.
The TPSI2140-Q1 is specifically designed to support dielectric withstand testing. In a high voltage system, a dielectric withstand test (HiPot) may be administered during the characterization, production or maintenance of the system to validate the reliability of the insulation barriers and galvanically isolated domains it contains. These withstand voltage tests intentionally stress the components spanning these domains and put them in an overvoltage condition. MOSFETs that are placed under these overvoltage conditions will enter avalanche mode and begin conducting current at a high voltage, dissipating high power and heating up. The design and qualification of the TPSI2140-Q1 was completed with this state in mind and supports up to 2 mA IAVA for 5 seconds intervals and 1 mA IAVA for 60 second intervals.
The dielectric withstand test voltage (VHiPot), the TPSI2140-Q1's avalanche voltage (VAVA), and the resistance (R) in series with the TPSI2140-Q1 should limit the avalanche current (IAVA) to the corresponding current limit depending on the test duration. In addition, the PCB design should follow the recommendations in the Layout Guidelines section to ensure adequate thermal performance to keep the junction temperature (TJ) below the absolute maximum rating of the TPSI2140-Q1.
Table 9-1 lists the Design Requirements for a typical insulation resistance monitoring application using the Chassis Ground Reference architecture and the TPSI2140-Q1 for switching.
PARAMETER | VALUE |
---|---|
VPACK Voltage (maximum) | 1000 V |
Primary side supply (VVDD) | 5 V ±10 % |
Dielectric withstand voltage test | 3500 V |
5 s | |
Surge voltage (IEC61000-3-5) | 2500 V |
RISO1 Selection
In order to protect the TPSI2140-Q1, RISO1 must be sized to limit the current in an overvoltage condition. The amount of resistance required to protect the TPSI2140-Q1 depends on the amount of overvoltage applied. For example, during a dielectric withstand voltage test (HiPot) of 3500 V for 5 seconds, the S1 to S2 voltage will be clamped to 1300 V (VAVA minimum) by the TPSI2140-Q1 and the RISO1 resistance required to keep the current under 2 mA would be 1.1 MΩ.
If the high potential test lasts for 60 seconds, the RISO1 resistance must be doubled to 2.2 MΩ to keep the current below 1 mA.
DC Overvoltage | RISO1 Minimum (5 second intervals) | RISO1 Minimum (60 second intervals) |
---|---|---|
2000 V |
350 kΩ |
700 kΩ |
2500 V |
600 kΩ |
1200 kΩ |
3500 V |
1100 kΩ |
2200 kΩ |
4300 V |
1500 kΩ |
3000 MΩ |
To ensure a reliable supply voltage, TI recommends that a 100-nF ceramic capacitor be placed between the VDD pin and the GND pin of the TPSI2140-Q1. The capacitor should be placed as close to the device's VDD pin as possible < 10 mm.