The TUSB9261 is an ARM® Cortex® M3 microcontroller based USB 3.0 to serial ATA bridge. It provides the necessary hardware and firmware to implement a USB attached SCSI protocol (UASP)-compliant mass storage device suitable for bridging hard disk drives (HDD), solid state disk drives (SSD), optical drives, and other compatible SATA 1.5-Gbps or SATA 3.0-Gbps devices to a USB 3.0 bus. In addition to UASP support, the firmware implements the mass storage class BOT and USB HID interfaces.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TUSB9261 | HTQFP (64) | 7.00 × 7.00 mm |
Changes from H Revision (July 2015) to I Revision
Changes from G Revision (October 2014) to H Revision
Changes from F Revision (March 2014) to G Revision
I/O TYPE | DESCRIPTION |
---|---|
I | Input |
O | Output |
I/O | Input/output |
PU | Internal pullup resistor |
PD | Internal pulldown resistor |
PWR | Power signal |
PIN | I/O | DESCRIPTION | |||||||
---|---|---|---|---|---|---|---|---|---|
NAME | NO. | ||||||||
SATA_TXP | 57 | O | Serial ATA transmitter differential pair (positive) | ||||||
SATA_TXM | 56 | O | Serial ATA transmitter differential pair (negative) | ||||||
SATA_RXP | 60 | I | Serial ATA receiver differential pair (positive) | ||||||
SATA_RXM | 59 | I | Serial ATA receiver differential pair (negative) |
PIN | I/O | DESCRIPTION | |||||||
---|---|---|---|---|---|---|---|---|---|
NAME | NO. | ||||||||
USB_SSTXP | 43 | O | SuperSpeed USB transmitter differential pair (positive) | ||||||
USB_SSTXM | 42 | O | SuperSpeed USB transmitter differential pair (negative) | ||||||
USB_SSRXP | 46 | I | SuperSpeed USB receiver differential pair (positive) | ||||||
USB_SSRXM | 45 | I | SuperSpeed USB receiver differential pair (negative) | ||||||
USB_DP | 36 | I/O | USB high-speed differential transceiver (positive) | ||||||
USB_DM | 35 | I/O | USB high-speed differential transceiver (negative) | ||||||
USB_VBUS | 50 | I | USB bus power | ||||||
USB_R1 | 38 | O | Precision resistor reference. A 10-kΩ ±1% resistor should be connected between R1 and R1RTN. | ||||||
USB_R1RTN | 39 | I | Precision resistor reference return |
PIN | I/O | DESCRIPTION | |||||||
---|---|---|---|---|---|---|---|---|---|
NAME | NO. | ||||||||
SPI_SCLK | 17 | O PU |
SPI clock | ||||||
SPI_DATA_OUT | 18 | O PU |
SPI master data out | ||||||
SPI_DATA_IN | 20 | I PU |
SPI master data in | ||||||
SPI_CS0 | 21 | O PU |
Primary SPI chip select for flash RAM | ||||||
SPI_CS2/ | 23 | I/O PU |
SPI chip select for additional peripherals. When not used for SPI chip select, this pin may be used as a general-purpose I/O. | ||||||
GPIO11 | |||||||||
SPI_CS1/ | 22 | I/O PU |
SPI chip select for additional peripherals. When not used for SPI chip select, this pin may be used as a general-purpose I/O. | ||||||
GPIO10 |
PIN | I/O | DESCRIPTION | |||||||
---|---|---|---|---|---|---|---|---|---|
NAME | NO. | ||||||||
JTAG_TCK | 25 | I PD |
JTAG test clock | ||||||
JTAG_TDI | 26 | I PU |
JTAG test data in | ||||||
JTAG_TDO | 27 | O PD |
JTAG test data out | ||||||
JTAG_TMS | 28 | I PU |
JTAG test mode select | ||||||
JTAG_TRSTz | 29 | I PD |
JTAG test reset | ||||||
GPIO9/UART_TX | 6 | I/O PU |
GPIO/UART transmitter. This terminal can be configured as a GPIO or as the transmitter for a UART channel. This pin defaults to a general-purpose output. | ||||||
GPIO8/UART_RX | 5 | I/O PU |
GPIO/UART receiver. This terminal can be configured as a GPIO or as the receiver for a UART channel. This pin defaults to a general-purpose output. | ||||||
GPIO7 | 16 | I/O PD |
Configurable as general-purpose input/outputs | ||||||
GPIO6 | 15 | I/O PD |
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GPIO5 | 14 | I/O PD |
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GPIO4 | 13 | I/O PD |
|||||||
GPIO3 | 11 | I/O PD |
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GPIO2 | 10 | I/O PD |
|||||||
GPIO1 | 9 | I/O PD |
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GPIO0 | 8 | I/O PD |
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PWM0 | 2 | O PD(1) |
Pulse-width modulation (PWM). Can be used to drive status LEDs. | ||||||
PWM1 | 3 | O PD(1) |
PIN | I/O | DESCRIPTION | |||||||
---|---|---|---|---|---|---|---|---|---|
NAME | NO. | ||||||||
VDD | 1 | PWR | 1.1-V power rail | ||||||
12 | |||||||||
19 | |||||||||
32 | |||||||||
33 | |||||||||
41 | |||||||||
47 | |||||||||
49 | |||||||||
55 | |||||||||
61 | |||||||||
63 | |||||||||
VDD33 | 7 | PWR | 3.3-V power rail | ||||||
24 | |||||||||
51 | |||||||||
VDDA33 | 34 | PWR | 3.3-V analog power rail | ||||||
40 | |||||||||
48 | |||||||||
62 | |||||||||
VSSOSC | 53 | PWR | Oscillator ground. If using a crystal, this should not be connected to a PCB ground plane. If using an oscillator, this should be connected to PCB ground. See Clock Source Requirements for more details. | ||||||
VSS | 44 | PWR | Ground | ||||||
58 | |||||||||
VSS | 65 | PWR | Ground – Thermal pad | ||||||
NC | 37 | — | No connect, leave floating | ||||||
64 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD | Steady-state supply voltage | –0.3 | 1.4 | V |
VDD33/ VDDA33 |
Steady-state supply voltage | –0.3 | 3.8 | V |
Tstg | Storage temperature | –55 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
VESD | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1) | ±2000 | V | |
Charged device model (CDM), per JESD22-C101(2) | ±1500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VDD | Digital 1.1-V supply voltage | 1.045 | 1.1 | 1.155 | V | |
VDD33 | Digital 3.3-V supply voltage | 3 | 3.3 | 3.6 | V | |
VDDA33 | Analog 3.3-V supply voltage | 3 | 3.3 | 3.6 | V | |
VBUS | Voltage at VBUS PAD | 0 | 1.155 | V | ||
TA | Operating free-air temperature range | 0 | 70 | °C | ||
Industrial version | –40 | 85 | ||||
TJ | Operating junction temperature range | –40 | 100 | °C |
THERMAL METRIC(1) | TUSB9261 | UNIT | |
---|---|---|---|
PVP (HTQFP) | |||
64 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 30.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 11.0 | °C/W |
RθJB | Junction-to-board thermal resistance | 6.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 6.1 | °C/W |
RJθC(bot) | Junction-to-case (bottom) thermal resistance | 0.9 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DRIVER | ||||||
TR | Rise time | 5 pF | 1.5 | ns | ||
TF | Fall time | 5 pF | 1.53 | ns | ||
IOL | Low-level output current | VDD33 = 3.3 V, TJ = 25°C | 6 | mA | ||
IOH | High-level output current | VDD33 = 3.3 V, TJ = 25°C | –6 | mA | ||
VOL | Low-level output voltage | IOL = 2 mA | 0.4 | V | ||
VOH | High-level output voltage | IOL = –2 mA | 2.4 | V | ||
VO | Output voltage | 0 | VDD33 | V | ||
RECEIVER | ||||||
VI | Input voltage | 0 | VDD33 | V | ||
VIL | Low-level input voltage | 0 | 0.8 | V | ||
VIH | High-level input voltage | 2 | V | |||
Vhys | Input hysteresis | 200 | mV | |||
tT | Input transition time (TR and TF) | 10 | ns | |||
II | Input current | VI = 0 V to VDD33 | 5 | µA | ||
CI | Input capacitance | VDD33 = 3.3 V, TJ = 25°C | 0.384 | pF |
POWER RAIL | TYPICAL ACTIVE CURRENT (mA)(1) | TYPICAL SUSPEND CURRENT (mA)(2) |
---|---|---|
VDD11 | 291 | 153 |
VDD33(3) | 65 | 28 |
POWER RAIL | TYPICAL ACTIVE CURRENT (mA)(1) | TYPICAL SUSPEND CURRENT (mA)(2) |
---|---|---|
VDD11 | 172 | 153 |
VDD33(3) | 56 | 28 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
CXI | XI input capacitance | TJ = 25°C | 0.414 | pF | ||
VIL | Low-level input voltage | 0.7 | V | |||
VIH | High-level input voltage | 1.05 | V | |||
Ttosc_i | Frequency tolerance | Operational temperature | –50 | 50 | ppm | |
Tduty | Duty cycle | 45% | 50% | 55% | ||
TR/TF | Rise/fall time | 20% to 80% | 6 | ns | ||
RJ | Reference clock | JTF (1 sigma)(1)(2) | 0.8 | ps | ||
TJ | Reference clock | JTF (total p-p)(2)(3) | 25 | ps | ||
Tp-p | Reference clock jitter | (Absolute p-p)(4) | 50 | ps |