The UCC28951 controller is an enhanced version of the UCC28950. It is a fully compatible drop-in replacement for the UCC28950. The UCC2895x devices use advanced control of the full-bridge in addition to active control of the synchronous rectifier (SR) output stage.
ZVS operation ensured over a wide range of operating conditions, while the load current naturally tunes the switching delays of the secondary-side synchronous rectifiers(SR). This functionality maximizes overall system efficiency.
Easily get started with the UCC2895x 600W phase shifted full bridge design review/application note, SLUA560
The 24-pin, TSSOP package complies with RoHS requirements.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
UCC2895x | TSSOP (24) | 7.80mm × 4.40mm |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
ADEL | 14 | I | Dead-time programming for the primary switches over CS voltage range, tABSET and tCDSET. See Section 6.3.6 |
ADELEF | 13 | I | Delay-time programming between primary side and secondary side switches, tAFSET and tBESET. See Section 6.3.7 |
COMP | 4 | I/O | Error amplifier output and input to the PWM comparator. See Section 6.3.3 |
CS | 15 | I | Current sense for cycle-by-cycle overcurrent protection and adaptive delay functions. See Section 6.3.14 |
DCM | 12 | I | DCM threshold setting. See Section 6.3.12 |
DELAB | 6 | I | Dead-time delay programming between OUTA and OUTB. See Section 6.3.6 |
DELCD | 7 | I | Dead-time delay programming between OUTC and OUTD. See Section 6.3.6 |
DELEF | 8 | I | Delay-time programming between OUTA to OUTF, and OUTB to OUTE. See Section 6.3.7 |
EA+ | 2 | I | Error amplifier noninverting input. See Section 6.3.3 |
EA– | 3 | I | Error amplifier inverting input. See Section 6.3.3 |
GND | 24 | — | Ground. All signals are referenced to this node. |
OUTA | 22 | O | 0.2A sink and source primary switching output. |
OUTB | 21 | O | |
OUTC | 20 | O | |
OUTD | 19 | O | |
OUTE | 18 | O | |
OUTF | 17 | O | |
RSUM | 11 | I | Slope compensation programming. Voltage mode or peak current mode setting. See Section 6.3.11 |
RT | 10 | I | Oscillator frequency set. leader or follower mode setting. See Section 6.3.10 |
SS/EN | 5 | I | Soft-start programming, device enable and hiccup mode protection circuit. See Section 6.3.4 |
SYNC | 16 | I/O | Synchronization out from leader controller to input of follower controller. See Section 6.3.15 |
TMIN | 9 | I | Minimum duty cycle programming in burst mode. See Section 6.3.9 |
VDD | 23 | I | Bias supply input. See Section 6.3.17 |
VREF | 1 | O | 5V, ±1.5%, 20mA reference voltage output. See Section 6.3.2 |