Hello! My name is George Lakkas, Strategic Marketing Manager for Cloud Computing and Communications, DC-to-DC -to- Solutions.

Today's computing cloud infrastructure and communications systems, such as rack or blade servers and etherthnet switches, have several high-current rails up to 30 amps that require precise voltage regulation, high power density, high efficiency, low parts count, and excellent thermal performance. Traditionally, a step-down PWM controller with external power MOSFETs has been used to regulate these rails. TI's NexFET process and PowerStack packaging technology enable us to power the same rails using one integrated FET converter-- IFET-- from the TI portfolio. Let's look at each one of the power design requirements and see how our PowerStack IFETs help meet the goals.

Parts count. If we look at a PWM and external-FET 20-amp schematic, we can see that a large number of external parts is required-- in this case, 44 components. Using one of our PowerStack DCAP-mode IFETs reduces the number of total components to 23-- a 48% reduction. This represents significant savings in PCB area and solution cost.

PCB area and power density. Based on the previous example, we see that the power density is also dramatically increased. We replaced four SO-8 MOSFETs and a PWM controller with a single-chip IFET in 5-by-6 QFN. This represents a 78% reduction in IC footprint for the same output power. Even when the PWM controller is placed on the bottom side of the PCB, there is still 75% PCB area reduction on the top layer.

So what about the power density? PowerStack IFETs can deliver upwards of 30 watts of output power, with excellent thermal performance, in 0.6 square inches. Thermal performance. In this example, the IFET delivers 30 watts of output power in 0.6 square inches at room temperature with no airflow. And the case temperature is a very manageable 60 degrees Celsius.

So how is it possible for this power-supply chip with onboard power MOSFETs to handle the output power and power dissipation in a small, 5-by-6 QFN package? This is possible because of TI's NexFET technology, combining low Rdson and low gate-charge MOSFETs, the optimized high-side, low-side FET design for synchronous back applications, and then advanced packaging technology called "PowerStack."

PowerStack is a source-down stack die packaging technology which stacks the high-side FET and low-side FET together and integrates them into one single package. This way, the source of the high-side FET is directly connected to the drain of the low-side FET die, and the source of the low-side FET is on top of the ground pad. Therefore, package-induced low-side drain inductance and source inductances for both high-side and low-side FET are significantly reduced. This enables lower switching loss and significantly higher power density versus designs using PWMs and external MOSFETs.

Also, the top-layer PCB layout is simpler, and the thermal dissipation is also better and easier, due to the copper clips inside the package and the ability to sink the dissipated heat into the internal PCB ground layers. Due to these advantages, IFET efficiency can approach 95% at output power levels of 70 watts with a 12-volt input bus-- efficiency previously not attainable with single-chip IFET solutions.

Designs using our DCAP mode TPS53k PowerStack IFETs are simple and require few external components. So I'd like to take you through the external component selection for a 14-amp steady-state back design, using the TPS53319 IFET and organic or special polymer output capacitors, bulk capacitors.

First, we need to decide the operation mode and soft-start time of the converter. Using table 1, we choose the connection for either Auto Skip mode, where the converter is always in automatic echo mode, during which it turns the internal synchronous FET off in response to a light-load condition, or Forced Continuous Conduction Mode-- FCCM-- where both FETs are switching, regardless of the load current. Using the R-mode resistor values, we also select the soft-start time.

To select the switching frequency, from 250 kilohertz to 1 megahertz, we use table 2, with a single resistor connected, accordingly, or left open. We then select the output inductor. The inductance value should be determined to give a ripple peak-to-peak current of approximately one quarter to one half of the maximum output current. Larger ripple current increases upward ripple voltage and improves signal-to-noise ratio while helping to ensure stable operation but also increases inductor core loss, increasing heat, and power dissipation.

Using one-third ripple current, to maximum output current ratio, the inductance can be determined by question 1. We need a low DC resistance or DCR inductor for high efficiency. We also need to have headroom above the peak inductor current before saturation. We don't want the inductor to saturate, as this will cause the inductor to act as a short circuit and not an energy-storage device. The peak inductor current can be estimated by equation 2.

Next is selecting the output capacitors. When using DCAP-mode IFET converters, in order to ensure loop stability the output capacitance and capacitor effective series resistance-- ESR-- should satisfy equation 3, where the 0-dB frequency or F0 is lower than one quarter of the switching frequency.

The output capacitor is chosen to minimize output noise voltage and to guarantee regulation during transient loads when the output current is changing from low value to high value and vice versa. The value, ESR, and ESL of the output capacitor determines the magnitude of undershoot or overshoot during a transient. To determine the output capacitors-- CO, in equation 3a-- we need to know the load current step, target allowed undershoot or overshoott-- Vunder or Vover-- maximum duty cycle of the converter, output inductor, and input and output voltage.

The voltage undershoot, voltage overshoot, and current step are typically given, the output inductor value has just been calculated, and the duty cycle is specified in the IFET converters' data sheet or can be calculated using the minimum on time and desired switching frequency. The top equation in 3a determines the output capacitance needed to meet the undershoot. Vin minus Vout is the voltage across the inductor when the load steps up.

The bottom equation in 3a determines the output capacitance to meet the overshoot. In this case, the voltage across the output inductor is only the output voltage-- Vout-- since the switch node is connected to one side of the inductor and is essentially ground-- 0 volts-- due to the low-side FET being on.

To improve converter output ripple jitter, we use equation 4 to determine the output capacitance ESR. D is the converter duty cycle. The required output voltage ripple slope is approximately 10 millivolts per switching period and is the voltage ripple at the converter voltage feedback-- VFB-- pin.

In order to calculate the values of the output voltage resistor divider, we need to assign a value for R2 to obtain R1. R1 is the resistor connected between the VFP pin and the output, and R2 is connected between the VFP pin and ground, as shown in figure 1. Recommended R2 value is from 10 kilohms to 20 kilohms, so we use this to determine R1 as in equation 5.

Last but not least, let's select the over-current protection setting resistor to set the current limit of the converter. This can be determined by equation 6, where Rtrip is in kilohms and we already know the inductance, switching frequency, input and output voltage, and desired current limit. The resulting design circuit is shown here.

The total number of external components for the complete power supply, including the TPS53319, is only 20. Today, we have demonstrated how TI's PowerStack IFET converters can replace PWMs and external FETs in high-current rails while delivering high efficiency, reduced PCB area, increased power density, and excellent thermal performance, with simple, external component selection. The TPS53k high-current IFET converter family includes the TPS53318, TPS53319, TPS53353, and TPS53355 that are all DCAP-mode control and pin-to-pin compatible.

All solutions are supported with design tools, models, and reference designs, including TI's popular WEBENCH design tool. For more information, please visit the URL on the screen.