Hello and welcome to this short overview of C2000 developments in digital power control. My name is Richard Poley and I'm in the C2000 System Solutions team. There are three parts to this presentation. First we will review the basic requirements for MCU control of a digital power system. Next we will go into details of some of the enhancements made to the latest C2000 devices to support digital power control, including changes to the control or accelerator as well as to the analog and PWM peripherals. Finally, we'll take a look at two recent digital power development kits, a high voltage solar micro inverter and a bi-directional DC-DC converter.

This diagram shows a high level block diagram of a digitally controlled power supply. In this case, an AC/DC telecom rectifier controlled by a C2000 MCU. PWM outputs from the MCU are shown as red tags while the analog feed back connections to ADC inputs are shown as green tags. Mains power entry is on the left followed by a diode bridge rectifier. This is followed by a power factor correction stage comprising two parallel connected boost converters.

The purpose of the PFC is to make the input current profile follow that of the input voltage, a function mandated by law in many countries for equipment above a certain power level. The PFC stage is followed by an isolated Phase Shift Full Bridge converter with active secondary side rectification which regulates the 48 volt output. The PWM patterns and timings for this stage can be very complicated. Notice that some of the MCU connections must pass across the isolation barrier.

The MCU is situated on the primary side. So in this case, two PWM signals and two analog signals must be isolated. If we stand back from the circuit diagram, we realize that the MCU simultaneously controls two very different power stages. Precise timings must be maintained on the PWM edges and on the analog sample points. And a control [? laws ?] must be computed with very low latency to keep pace with the switching frequency.

By no means all MCUs are capable of performing these operations. However, the C2000 platform has been designed for this type of application and does so well. Let's take a look at the architectural features which are needed to support digital power control.

Firstly, we need a high speed analog to digital converter which can be synchronized to the PWM wave forms to ensure voltage and current samples are taken at the correct instance of time. We also require a high performance computational engine, or CPU, capable of computing the control law extremely quickly. Note that when it comes to digital control, not all CPUs are created equal. Architectures which are optimized for general purpose tasks or for streaming data applications such as audio or video, often do not perform well when processing single data samples.

Thirdly, we need a flexible PWM pattern generator capable of being configured to support the 20 or so common power supply typologies. Actually, this is not as simple as it sounds and presents a complex set of problems for the IC designer. We will look at some of the difficulties later and explain how the C2000 PWM architecture solves them.

These three requirements are what you might immediately think of for digital control. However, control of power electronics may also require features which cannot be implemented in software. An example is peak current mode control in which PWM edge transitions are determined by the instantaneous current flowing in an inductor. To support this, the PWM must be capable of responding to an asynchronous trigger from an analog comparator. Additional features such as slope compensation may also be required.

This slide shows a high level block diagram of one of the newest C2000 devices. The architectural features mentioned in the previous slide are all visible. First, the device comprises multiple high speed ADCs which can be triggered directly from the PWM generators. The analog module contains a number of internal comparative subsystems, each capable of implementing peak current control loops together with slope compensation.

There is a high performance CPU and a parallel control law accelerator, or CLA, which is optimized for low latency computation of the control law. Lastly, the device contains a number of highly configurable PWM modules which will be explained later. The device also contains a number of basic life support features such as clock generators, power supply supervisors, and communications ports. These combine to provide a low cost and easy to use solution for digital power control.

Next, we'll take a look at some of the enhancements for digital power control in new C2000 devices. We'll begin by reviewing briefly some of the enhancements made to the control law accelerator. The first is an additional addressing mode which enables easier indexing into data structures. The indirect offset addressing mode shown applies a temporary offset to an auxiliary address register, either MAR0 or MAR1.

Following the data read, the original register address is left unchanged. This is in addition to an existing similar mode which auto incremented the MAR register after the data address was accessed. Both the program counter and the task vectors are now 16 bits in length. This allows access to the low 64 kiloword of memory space and, in particular, to the six two kiloword blocks of local shared RAM, LS0 to LS5. These memory blocks include parity error detection and are password protected. The memory available for CLA use has increased from six kiloword on F28035 to 12 kiloword on F28377.

New registers have been added to configure the LS memory blocks for CLA use, as well as to determine whether they are used for data or program storage. Task offsets as well as the task trigger sources are now configurable using new registers, which would normally be set up on system initialization. The allocation of a separate task to initialize the CLA is no longer necessary.

Finally, a restricted syntax C compiler is now available for the CLA. For more information on the CLA and other hardware accelerators in the C28x core, see the accelerator session in this year's MCU deep dive event.

Some newer C28x devices include a high resolution capture peripheral, or HRCAP for short. One of the uses for this peripheral is to enable low cost isolation of an analog signal. The diagram shows how this might be accomplished. Here an analog input to be measured is applied to one input of an analog comparator. The other input is connected to a fixed frequency sawtooth waveform. So the comparator output is a pulse width modulated digital signal where the duty cycle of each pulse conveys the amplitude of the incoming signal.

Digital signals are much less costly to isolate than analog ones. For example, using a low cost opto-isolator, as shown here. The output of the opto-isolator is connected directly to the HRCAP peripheral where the duration of each pulse can be measured with a precision of around 150 picoseconds. In this way, we achieve isolation of an analog signal at very low cost.

The latest F2837x devices include multiple ADCs, configurable in either 12-bit or 16-bit mode. This design allows multiple analog channels to be sampled simultaneously without using multiple sample and hold units, and provides a lot of flexibility to the user when selecting input channels and trigger sources.

The analog sub system also contains a number of general purpose buffered 12-bit [? DACs. ?] There is also a temperature sensor and an array of comparative subsystems which might be used for fault detection or current mode control. We will examine these in more detail later.

Notice that the ADC inputs are shared with those of the comparator subsystems. For instance, the positive and negative inputs of comparator subsystem one are shared with channels two and three of ADC A. Each ADC is associated with four post-processing blocks, or PPBs. These blocks can be assigned to any of the ADC channels and perform automatic post-processing on the conversion results.

For example, a PPB can automatically remove a known offset from an ADC result. It can also compute the signed result of a server error using a programmable offset register. The result can be compared with high, low, and zero crossing thresholds to either trip a PWM module through the digital compare sub module in the PWM subsystems or generate a CPU interrupt.

Finally, the PPB can measure the delay between the ADC receiving-- a start of conversion signal-- and the actual start of the sampling process. Such delays arise when the ADC is already converting a different channel or has a series of higher priority channels to convert before starting the one requested. This feature time stamps a free running counter when an SOC signal is received and again when the conversion begins. The difference between the two time stamps gives us the SOC delay.

The comparator subsystem fitted to the latest generation of C28x devices combines the features required for over and under voltage protection with those of peak current mode control. Effectively, the same comparator subsystem can be used for either task. For fault protection and inverter applications, it is necessary to enforce two comparative thresholds, upper and lower limits which combine to provide a safe window of operation. Different fault conditions could cause the inverter output to move in either direction, so we need two independent comparators to achieve this.

In peak current mode control, we typically use only one comparator with a negative input supplied by an internal [? DAC ?] coupled with an internal ramp generator for slope compensation. The polarity of each comparator output can be selected by the user. Also, the outputs can be independently filtered by a programmable majority volt filter with two independent taps, allowing the user to trade off the degree of filtering with the speed of the filter response.

One filter tap is routed through the output crossbar. For example, to the GPI [INAUDIBLE], while the other passes through the PWM crossbar where it would typically be used to trip one or more of the PWM outputs.

The PWM generator is probably the most complicated peripheral in the device. The design has evolved over several years to cope with the demands of the many and diverse power supply typologies. Before discussing details of the latest enhancements, let's take a moment to remind ourselves of the basic PWM subsystem architecture.

Every C28x device contains a number of PWM modules, perhaps six or 10 depending on the part number. Each PWM module can be broken down into eight sub modules, five of which perform the most fundamental operations of PWM pattern generation. Here we present a simplified overview of these five submodules.

First, the time based module provides a programmable 16-bit counter which can be synchronized with the counters in adjacent PWM modules. The count rate and counter period define the frequency of the counter output, and therefore of the PWM patterns. The time offset of one counter relative to another can be changed using a phase shift register.

The time based submodule is followed by a block containing four digital comparators, each of which produces a logical one at its output when the incoming count equals the comparator value. In this way, a series of four pulses is produced as the timebase counter sweeps through its full range.

The action qualifier submodule assigns specific events to each comparator pulse. For example, a low to high PWM image, an interrupt, or a start of conversion signal for the ADC. In this diagram we see a classical active high complimentary pair of PWM wave forms which might be used to drive a push pull MOSFET pair.

In such power stages, dead-band must be applied to the PWM wave form to avoid dangerous shoot-through conditions. Rising and falling edge dead-band timings can be independently adjusted by the user. The last module shown here is the trip zone module which provides an asynchronous path to switch off the PWM pattern in the event of a fault condition, or during current mode control.

We will now explore some of the most important enhancements to the PWM architecture. Among these, the introduction of a delayed trip mechanism allows dead-band to be applied in peak current mode control with no software overhead. Two features, one shot and global reload and simultaneous rights across registers have helped to support the complex PWM timings which appear in multi-phase power applications. The shadowing of action qualifier registers now permits PWM patterns to be changed safely from one mode to another without stopping the PWM.

Finally, the increase in resolution of dead-band timing helps with control in high frequency soft switching applications, such as the Phase Shifted Full Bridge topology shown in an earlier slide. The first two enhancements shown here are present in the latest F2837x Delfino devices while the last three were introduced on the F28M35 Concerto platform. Let's look at each of these enhancements in more detail.

In this slide we see a simple synchronous buck converter operating in peak current mode control. PWM 2A and 2B operate as a complementary pair. The inductor current rises linearly when the upper switch, controlled by PWM 2A, is turned on. This PWM output is switched off when the inductor current reaches a level defined by the current loop controller. However, as it does so, PWM 2B must be prevented from turning on until the upper switch has ceased conducting.

On earlier devices, this dead-band delay had to be implemented using software timings. However, it is now automatically accounted for by hardware inside the trip zone submodule.

In this slide we see a slightly more complicated example of peak current mode control. In this case, applied to a Phase Shifted Full Bridge topology. This type of power converter operates in four distinct phases according to the states of the switches in each power leg. In two of the four phases, indicated by the blue rectangles in the timing diagram, power is being transferred to the secondary side. In the other two phases, the transformer primary winding is effectively shorted across either the DC bus or across ground.

The transition out of a power stage is determined by the instantaneous current flowing in the transformer primary winding. Notice that this requires the delay trip feature of the previous slide to be applied on both the rising and falling edges of the Q2 PWM output. The delayed trip is implemented in such a way as to make this possible.

Next we will look at some of the issues which arise when controlling multi-phase power typologies. Firstly we see an example of a power converter in which two PWM patterns are frequency modulated but must remain aligned in phase. We see only the timebase counter outputs of the two PWM modules. The adjustment of frequency is typically performed in an interrupt service routine which runs asynchronously with the PWM timings. The interrupt could therefore occur anywhere within the PWM cycle.

In the first case, there is sufficient time for the ISR to update all the registers in both PWM modules before the shadow to active reloads which take place when the counters are zero. However, in the second case, only the registers in the upper PWM module could be updated before reload, while those in the lower module miss their reload point and must wait another PWM period before their shadow to active reload.

This is a potentially destructive condition for the power stage. A solution to this is to link together similar registers in different PWM modules such that an update in one PWM or module is replicated simultaneously in another. In this way, all the registers are updated together in a single write and the timing contention shown in the diagram cannot occur.

A related but different issue can occur in typologies where there is a deliberate phase offset between PWM channels. Here we again see the time bases of two frequency modulated power stages. But now a fixed phase offset must be maintained between them. Duty cycle, frequency, and phase shift must all be controlled simultaneously. Again, the control interrupt is asynchronous with the PWM waveforms.

Depending on the timing of the register writes, it is possible that a partial update of the PWM registers will be completed. But the period register is not updated before the shadow to active reload, resulting in a miss of the period event and a PWM output which is locked high or low until the timebase counter wraps around. This is usually a destructive situation.

The solution is to ensure that the shadow to active register reloads are synchronized across different PWM modules, and a feature which enables this is called global and one shot reload. The implementation of global and one shot reload is shown in this diagram taken from the F28377 device user's guide. The existing shadow to active reload strobe is shown in the bottom part of the diagram. This could be the period or duty cycle update strobe. The upper part shows the enhancements which force a global shadow to active reload from a common source, which can occur as either a one shot event or on a cycle to cycle basis using a 3-bit counter.

An important enhancement to the PWM architecture allows the PWM pattern itself to be modified safely without stopping the PWM waveforms. In the example shown here, a control interrupt occurs at the counter zero point. The ISR might need to modify the action qualifier registers to temporarily disable the phase by switching off both PWM outputs. To do this, the ISR writes to the action qualifier registers to assign the appropriate actions to the compare events.

On newer devices, the action qualifier registers are updated automatically on the next counter zero point. So all the changes take place simultaneously. This allows a safe transition from one operating mode to another. An important use of this feature in digital power supplies is to support burst mode PWM and in PWM finning where some PWM pulses are dropped to improve efficiency under light load conditions.

Four other enhancements to the PWM architecture as shown here. The first concerns the blanking window feature of the digital compare submodule. This feature disables PWM tripping during a user selectable interval in the PWM cycle. This is useful if there are known to be current or voltage spikes present to which the PWM module should not react. The origin and duration of the blanking window are now both determined by 16-bit registers, giving a greater degree of flexibility than before over the blanking window timings.

The trip zone flags are now latched so that the cause of a fault trip can be determined even if the fault is present only for a very short time. There is more flexibility on PWM synchronization with the possibility to synchronize time bases from C and D comparator events in addition to the zero count and [INAUDIBLE] events.

Lastly, a change which is transparent to most users of the device. The mapping of the memory mapped registers which configure the PWM modules has changed. Originally register addresses were collected together according to the module so that all the registers relating to the same module occupied the same memory range. In use, it is typically the case that registers with similar functions in different PWM modules are updated at the same time.

On newer devices, PWM registers are grouped by function rather than by module. This simple change results in fewer data page pointer reloads inside the ISR, and therefore better code efficiency, especially in the time critical parts of the application code.

To close this presentation, let's take a quick look at two new digital power development kits based on the C2000 platform. The first is an example of a micro solar inverter. This kit uses a high gain fly-back typology with active clamp to boost the panel voltage from a few tens of volts up to 400 volts. The fly-back stage also implements maximum power point tracking, an algorithm which adjusts the output load depending on the output voltage of the photovoltaic cell to obtain maximum power transfer.

The isolated fly-back stage is followed by a grid connected single-phase inverter. The topology used here is two parallel buck stages, one each for the upper and lower halves of the inverter output. Switches P2B and P3B operate at 60 Hertz while switches P2A and P3A are duty cycle modulated at 50 kilohertz to generate the required output halfway form. This kit is currently available for purchase on TI's e-store.

The second development kit is an example of an isolated 400 watt bi-directional DC-DC converter. This type of converter is commonly found in electric and hybrid electric vehicles, as well as in industrial battery backup systems. The power flow is bi-directional, either from 400 volts to 12 volts or from 12 volts to 400 volts. The topology used is Phase Shifted Full Bridge with active secondary rectification in the former case and push-pull with active clamping in the latter case. Current mode control is implemented in both modes. The converter is controlled by a single F28035 device situated on the 400 volt slide.

Thank you for joining this presentation about C2000 enhancements for digital power. You can learn more about the C2000 platform at www.ti.com/c2000.