Hello, and welcome to this next video in the Designing with Delta-Sigma ADCs training series. This video will focus on the ADC sampling network and the analog front end. The input stage of an ADC is one of the most critical circuits to an ADC's performance. For this reason, some devices include a high impedance buffer at the ADC inputs to facilitate the signal chain design.

If an input buffer is not included with your ADC, there are several additional design considerations to make, in order to maximize system performance. Here are the main input signal chain components. The input signal chain will consist of some signal conditioning stage, followed by an RC input network, and lastly the ADC sampling inputs. Let's start by learning how the ADC inputs are sampled.

The inputs of a delta-sigma modulator feature a switched capacitor sample and hold circuit, like the one shown on the left. In this simplified diagram, the switched capacitor stage is comprised of two inputs switches, named S1, a differential sampling capacitor, CSAMPLE, and another switch, S2. In phase 1 of the sampling period, the S1 switch is closed, and CSAMPLE is connected to the external circuitry. Charge is transferred to CSAMPLE, and the voltage approach is the same level as the input signal. This is similar to the acquisition time of SAR ADC.

At the end of the sampling phase, the S1 switches open, and the voltage across the sampling capacitor is converted by the modulator. This is known as the conversion phase. The sampling capacitor is then discharged before the next sample, by closing S2.

The effective input impedance is due to the average current drawn by the switched capacitor network. The input impedance is often given in the data sheet as a typical value, Rnom, for some nominal modulator frequency, Fnom. The input impedance then scales with the modulator frequency used in your configuration. The point here is that the unbuffered ADC inputs are not high impedance, placing a greater demand on the input stage drive requirements.

Every time the ADC samples the inputs, the switched capacitor network draws current from the external signal chain and transfers charge to the internal sampling capacitor, CSAMPLE. Much of this current is sourced by the external differential capacitor, CDIFF. This is one of the key functions of the RC filter at the ADC inputs.

In this sense, CDIFF acts as a charge reservoir. By providing most of the instantaneous current, CDIFF helps to keep the input voltage stable during the sampling phase of the ADC. Meanwhile, the filter resistors, RFLT, are needed to keep the external drive circuitry stable. In addition to providing charge, the RC network also forms a pole and provides some low-pass anti-aliasing benefits as well.

The transfer of charge from CDIFF to CSAMPLE creates an initial voltage droop at the ADC inputs. The amount of droop depends on the differential input voltage and the ratio of CDIFF to CSAMPLE. As the differential voltage increases, so does this voltage droop.

To understand the expected voltage droop, consider the initial charge across CDIFF before the sampling phase begins. This charge, Q0, is equal to CDIFF times the initial differential voltage, VA. Meanwhile, CSAMPLE has a differential voltage of 0 volts, since it was recently discharged from the previous sample.

Once the sampling phase begins, S2 will open, and the S1 switches will close. Some of the initial charge across CDIFF will now be transferred to CSAMPLE, and the input voltage will droop to VB. This voltage will be the same for both CDIFF and CSAMPLE, as they are now in parallel. Q1, the remaining charge on CDIFF, is equal to CDIFF times the VB, while Q2, the charge on CSAMPLE, is equal to the same voltage times CSAMPLE. Together, Q1 and Q2 add up to equal the original charge, Q0.

Using these equations, we can see that the voltage droop is a product of the differential input voltage and the ratio of CDIFF to the total capacitance between CDIFF and CSAMPLE. Non-ideal impedances, such as the ESR and ESL of these capacitors, will affect this droop and subsequent voltage recovery. Generally speaking, aim to make CDIFF at least 100 times greater than CSAMPLE, such that VB is at least 99% of the original input voltage. Larger capacitors will keep the input nodes even more stable, but may also limit the signal bandwidth.

Once CDIFF is known, size the filter resistors to be as small as possible, while maintaining the amplifier stability. Too small of a filter resistor will lead to amplifier instability and degrades distortion due to inadequate input settling. Too large filter resistors leads to large gain error terms.

The differential input transient voltage can often be observed on an oscilloscope with an active differential probe. For a 0 volt input, there is practically no voltage droop, as the transfer of charge is nearly 0. As differential voltage increases, the transient voltage also increases. For a given application, it is important to evaluate the system's performance under the largest expected input conditions, to determine the worst case settling error. The limitations of most oscilloscopes will prevent you from measuring the complete settling behavior down to the microvolt level. But any significant ringing should at least become apparent.

The goal of the input drive amplifier is to restore the voltage across CDIFF such that the voltage is fully settled before the next sample. Fully Differential Amplifiers, or FDAs, are great for driving the differential unbuffered inputs of delta-sigma ADC for a couple of reasons. One, they can accept either single ended or differential inputs and convert the signal to a differential output. Two, the differential output can be centered around a mid-supply common mode voltage without any additional circuitry. This allows both the inverting and non-inverting outputs of the FDA to swing equally between the supply rails and utilize the full scale range of the ADC. Next, we'll take a look at some key amplifier specifications to consider when choosing your input amplifier.

Three important specifications to consider are gain bandwidth product, voltage noise density, and quiescent current. Shown here are three fully differential amplifiers from the same product family. For different levels of speed and noise performance, each one offers a trade-off with power and price, which can be important as well. Let's look at how gain bandwidth product effects our input voltage settling and consequent ADC performance.

An amplifier with more gain bandwidth will be able to provide the instantaneous current demanded by the ADC inputs more quickly. As a result, the input voltage will settle faster. This is something to consider for both DC and AC applications.

On the left is the transmit response, as seen at the inputs of an unbuffered delta-sigma ADC. The amplifier driving the ADC is the THS4541 with a gain bandwidth of 850 megahertz. The ADC is sampling the inputs at 16 megahertz. A full-scale DC input is applied to the THS4541, such that the initial voltage droop and subsequent recovery will be the greatest.

After each sample, the THS4541 is able to fully settle the input voltage very quickly, with hardly any overshoot or ringing. On the right is an FFT taken with a full-scale sine wave applied to the input of the same circuit. From this plot, you can see how there is very little harmonic distortion, as the highest harmonic is only at minus 126 dB.

Now, let's look at the same results using the THS4551, with a gain bandwidth of 135 megahertz. As the gain bandwidth of the input amplifier stage decreases, the transient response shows a longer settling time. In the frequency domain, this leads to greater harmonic content and degraded distortion performance.

The THS4531A has the least gain bandwidth of the three amplifiers. Clearly, the transmit response shows a much slower settling time, which results in the largest harmonics and the worst distortion. In each of these cases, the FDA is driving the same RC network, and the ADC is sampling at the same modulator rate.

Spurious Free Dynamic Range, or SFDR, is the difference between full-scale and the highest spur in the frequency spectrum, besides the fundamental. SFDR is an indication of the distortion in an ADC system, as harmonic content will increase with the decrease in distortion performance. This plot shows the SFDR results from the same three FDA solutions. The modulator sampling frequency, fMOD, was swept from 16.384 megahertz down to 100 kilohertz. The input signal amplitude was kept constant at minus 0.5 Db below full scale, where distortion is expected to be the worst.

As previously shown, an amplifier with lower gain bandwidth will struggle to fully settle the voltage across the inputs at higher fMOD frequencies. As fMOD is reduced, the inputs have more time to settle, and the distortion performance of the system improves. This shows that a lower power amplifier with less gain bandwidth can be used to meet higher distortion targets at slower sampling rates.

Many customers will ask whether scaling the modulator frequency has the same impact on noise performance. The answer is yes, but only a little. The SNR in a delta-sigma ADC system is dominated by the noise in the signal chain, including passive and active components, as well as the oversampling ratio, or OSR, in the digital filter. For every doubling of the OSR, you can expect an average SNR improvement of about 3 dB.

Reducing the modulator frequency does decrease the output data rate, and thus the digital filter bandwidth. As a result, some of the input source noise is filtered out at lower frequencies, while it passes through and dominates at higher frequencies. This trend holds constant for all three FDA solutions. Clearly, it is the difference in the amplifier broadband noise density that has the most impact on SNR. The gain bandwidth product of these amplifiers really has no impact on noise performance.

When it comes to choosing the right amplifier to drive a delta-sigma ADC, trade-offs can be made to optimize the signal chain for the specifications you care about most. In low noise applications, start by choosing the lowest noise amplifier that fits within your power budget. Also configure the ADC to use the highest oversampling ratio available, while maintaining the desired data rate and signal bandwidth.

In low distortion applications, the gain bandwidth product will be the most important. Use the highest gain bandwidth available, while still meeting your power and noise targets. Remember that the modulator frequency can be scaled down to meet the distortion targets, while using an amplifier with less gain bandwidth.

Finally, in low power applications, gain bandwidth and noise will be sacrificed for the amplifier which offers the lowest power. The master clock input, the modulator frequency, and the OSR can all be scaled in an ADC, to adjust analog and digital power consumption.

A great schematic can be ruined by a poor layout. Consider the following guidelines when designing the PCB layout for your amplifier. First, place the differential output capacitor, CDIFF, as close as possible to the ADC inputs, to minimize the impedance and inductance of the traces. For differential measurements, make sure the input traces are matched as well.

Amplifier input pins are generally high impedance and more susceptible to noise pickup. Keep any feedback components routed closer to the inputs, to minimize noise coupling. As always, sensitive analog circuitry should be positioned away from the digital traces and switching supplies. Finally, make sure to provide a low impedance path and proper decoupling for the amplifier supplies.

Here are a few tips for debugging poor amplifier performance. Start by reviewing key input amplifier specifications, such as the input common mode voltage range and the output voltage swing. Make sure that all data sheet conditions are satisfied. Also ensure that you have adequate decoupling capacitors on all supplies.

If these don't resolve the issues, try some of the following tests. To ensure that the amplifier output is not too close to the supply rails, try adjusting the output common mode voltage, or increasing the supply range, in order to give the amplifier more headroom. This is sometimes helpful with output clipping or distortion issues.

One useful tip is to refer to the conditions used to specify the open loop gain, or AOL, as the linear region of output swing. If you suspect the ADC input voltage is not fully settling, probe the ADC inputs with an oscilloscope and look for any obvious overshoot or ringing. You may need to trigger the oscilloscope on the ADC clock for a consistent signal. Then try reducing the clock frequency to allow the inputs more time to settle, and see if performance improves. You may also consider increasing the RC filter components, or substituting an amplifier with more gain bandwidth.

Well that's all for now. Stay tuned, for additional videos in this series on designing with delta-sigma ADCs.