I2C & I3C level shifters, buffers & hubs

Solve voltage-level mismatches and prevent heavy bus capacitance loading

parametric-filterView all products
Our I2C level shifters, buffers and hubs strengthen your I2C bus signal and prevent heavy bus-capacitance loading. These products also help solve voltage-level mismatches because the designer can use the latest peripherals by adding level shifters that enable different voltage levels on host and device.

Featured I2C level shifters, buffers & hubs

What makes our I2C level shifters, buffers and hubs different?

checkmark

Diverse portfolio of solutions

Diverse features such as rise time accelerators, stuck bus recovery and internal current sources allow you to find a solution for any application while meeting I2C requirements.

checkmark

Innovative solutions

Continuous improvement and new solutions that allow for faster data rate (up to 12.5 MHz) and small packages (X2SON) that allow for you to design innovative solutions.

checkmark

Cost-effective and reliable

Our IxC devices meet l2C and I3C standards and are designed to provide reliable solutions that help reduce design cost by saving board space (small packaging) and reducing external components.

Technical resources

Application note
Application note
Why, When, and How to use I2C Buffers
The I2C communication interface has been standardized for reliable communication. One of those standards is max bus capacitance.  Learn how the I2C buffer is a solution for systems requiring a larger bus capacitance. 
document-pdfAcrobat PDF
Resource
Resource
Intro to I2C: what the Internet doesn't tell you 
What initial internet searching will tell you is that I2C makes it easy for system designers to implement robust system controls. Not only is this protocol useful, but there are many device functions that can benefit your system. 
Application note
Application note
I2C Dataline Handoff Delay
Adding a buffer device can introduce propagation delays and result in visible SDA handoffs. The TCA9517 device, an I2C static voltage offset buffer, is examined for its propagation delay which can result in the SDA handoff delay.
document-pdfAcrobat PDF

Design & development resources

Design tool
I2C designer tool
Use the I2C Designer tool to quickly resolve conflicts in addressing, voltage level and frequency in I2C based designs. Enter master and slave inputs to automatically generate an I2C tree or easily build a custom solution. This tool will help designers save time and comply with the I2C standard (...)
Evaluation board
TCA39306 evaluation module low voltage I²C level-shifter

This EVM provides configurable loading conditions through adjustable pull up resistors and bus capacitance which allows designers to easily test the performance of this device in their system.

Simulation tool
PSpice® for TI design and simulation tool
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)