MOSFET 101

Hello, my name is Brett Barr. I'm a product marketing engineer for Texas Instruments, specifically handling our 40 to 100 volt NexFET power MOSFET devices. Today, we're going to be talking about the MOSFET data sheet. And specifically, we'll be discussing avalanche ratings and what those mean.

So a brief history, this parameter Avalanche Energy and UIS current was actually not added to MOSFET data sheets until the 1980s. And that's when it became not just a data sheet parameter, but a parameter that a lot of customers demanded that the FET be tested to before it was sent into production, particularly, when the MOSFET is being recommended for power supply or switching applications. It's a crucial parameter for weeding out weaker devices or devices more prone or susceptible to failure.

So it wasn't long before this parameter was added to the data sheet, before marketing engineers like myself started figuring out that the higher the rating, the more competitive the part looked and started figuring out how to play games with the parameter by varying some of the values that the parameter was tested at. And I'll talk about that more later. But in general, the higher the avalanche energy, the more rugged and robust the device is. So larger is better.

Most FET data sheets will include this parameter in their Absolute Maximum Ratings Table, which in our case, is located right on the front page of our data sheet. Specifically, you can see the parameters here is Avalanche Current and Avalanche Energy, Eas. So Avalanche Energy is defined as the amount of energy the MOSFET can withstand when it is set into avalanche mode or its breakdown voltage is exceeded.

And that value is determined by the Avalanche Current, which is done during an Unclamped Inductive Switching test. So when people are talking about UIS current, they are talking about Avalanche Current. And an Unclamped Inductive Switching test is conducted to determine the current and thereby the avalanche energy that will cause the MOSFET to fail. As I mentioned, these values are highly dependent on test parameters, specifically, this condition of the inductor value used during the test.

Here, in the lower left corner, you see a UIS test circuit set up. So we have a voltage source in series with an inductor, L, also in series with the device under test, in this case, our MOSFET. And over here, you have the gate controller of the FET in series with a gate resistor. On the right, you have, taken from our characterization lab, our fancy LTC55140 tool. This is the tool that we use to characterize the UIS rating of the FET.

And that capability is then used to determine not only the FET data sheet rating, but also the value used to screen the FET during final test. What's effective or helpful about this tool is that it allows us to vary several parameters. So when the field comes in and we get questions from customers, we say FET vendor A test under these conditions. You test under these. What's a true apples to apples comparison? This allows us to give that to them.

So we can vary the inductor value from 0.2 to 160 millihenries. We can vary the drain voltage on the FET from 10 to 150 volts. So that allows us to exceed even our 100 volt breakdown voltage FETs. And, of course, we can marry the drain current from 0.1 to 200 amps. That's the UIS current that the FET is going to be exposed to during the test. We can also vary the temperature, negative 55 to 150 degrees. And that's a handler that allows us to actually vary the case temperature of the FET under test.

So there's four stages that comprise a standard UIS test. So let's go through them. The first stage is this pre-leakage test, where the supply voltage biases the drain of the FET. And basically, we're just trying to make sure the FET is behaving in the manner that we would expect, that the FET is functioning properly. So FET is turned off. It's blocking the supply voltage without seeing any extreme leakage current going through the FET.

The second stage, we call the Avalanche Current ramp up, where we turn on the FET so the drain voltage drops. And the current through the inductor steadily increases at a constant di dt. So we're charging up the inductor. During the third stage, the avalanche test, this is where we actually avalanche the FET. So what we do is we turn off the gate voltage, so the FET is turned off. That creates a huge di dt through the inductor, which makes the drain voltage of the FET swing high above the breakdown voltage of the FET.

So the FET is sent into an avalanche mode. During that event, the FET absorbs all of the energy that was built up in the inductor. And then the FET remains off as we conduct the fourth stage, which is a post leakage test. So after the FET has incurred this avalanche event, we test, once again, to make sure that the FET is still behaving properly. And if it is, then the FET has passed the test.

So what we do then is we repeat this process, so it's an iterative process. Each time, we steadily increment the UIS current up a notch until we reach the point where the FET fails this post leakage test. And that's what we know or recognize to be the full UIS current capability of the MOSFET.

Once we've measured the UIS current that the FET is capable of handling up until failure, it's very easy to take that value and then determine the amount of energy that was dissipated into the FET during avalanche. So if we assume that all of the energy that was stored in the inductor during the Avalanche Current ramp up was then dissipated into the MOSFET, that energy can be calculated from E equals one 1/2 LI squared.

EE 101 tells us that the amount of energy in an inductor is equal to 1/2 the inductor value times the current squared that is just running through the inductor. So we have measured 125 amps for this device. This is our CSD18502KCS. This is a 40 volt TO220. Once we have this UIS current, we can use this inductor value to calculate the energy which was dissipated, which was 790 millijoules.

Now, as we increase this inductor value, we see an interesting phenomenon where the amount of current that it takes to fail the FET, or the maximum current that the FET can handle, actually decreases. But this dollar order of magnitude increase in inductor size actually offsets this decrease in current in our energy equation such that the energy value actually increases.

And this is where we get to some of those games that I was talking about earlier where other vendors, other FET vendors, will deliberately use a higher inductor value on their data sheet to artificially increase the amount of energy that the FET appears to be able to handle during the avalanche event. So all of TI's MOSFETs are done at 0.1 millihenry inductor value. And that's because the higher the Avalanche Current, the more stressful the test. And we want to screen out as many weak devices as we can during final test.

But this isn't just the value that we use during final test before the FET goes into production. This is also the value that is then used in our data sheet. Now, we take this value, and we derate it in order to provide a little bit of margin. So we take this 125 amps. In this case, we derate it by 65%. And in all cases, 65% is the number that we use.

And that gives us the number that you see on the data sheet of 81 amps. And this 81 amps is also the current that is used to calculate the energy that you see on the data sheet as well. Final test, actually, tests this value to 70% of the measured capability as opposed to 65%, just so that you get a little bit more margin in between the data sheet rating and what the part was tested to.

The last thing I'd like to highlight is this figure up here that appears on all of our power MOSFET data sheets, at least those recommended for switching applications. And it's usually figure 11 in the data sheet. And what we show is Avalanche Current Capability versus Time Spent in Avalanche. And we show it at a case temperature of 25 degrees, and then we increase the case temperature to 125 degrees. Take the same test in order to show the difference.

And in this case, case temperature of the MOSFET is very close to the actual junction temperature of the silicon die. Now, as you increase the temperature of the die, you'd expect to see some degradation as you increase temperature, right? But if you see too much degradation, that's actually a symptom of an inherently weak device. So from a design perspective, we try and target less than 30% degradation from 25 to 125 degrees.

If you come down here and look at what was actually measured capability of us and several competitors, you see our CSD17307Q5A, at 25 degrees, capable of handling up to 23 amps. UIS current, at 125 degrees, closer to 20 amps. So about 16% degradation. If you look at competitor C and competitor B, both of them fall within about that same range, right? Certainly less than 30% degradation from 25 to 125.

Now, if you come over and look at competitor A, you actually see a much larger delta. Whereas, at 125 degree junction temperature, the FET could only really handle about 30% of the Avalanche Current that it could handle at 25 degrees.

And I highlight this because this vendor actually had an issue where they went to market with this device as is, and then they had to correct the issue after the fact because they were seeing many failures in actual application. So this is just something to watch out for on other vendors' data sheets. What's this delta from 25 to 125? What's the degradation in terms of UIS capability?

So that's all I have. Thank you very much for listening. I hope you got something out of this. And for more information about our MOSFET devices, I would implore you to go to ti.com/MOSFET.