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ビデオ・シリーズ

プレシジョン ラボ シリーズ:LVDS

TI プレシジョン ラボ (TIPL) は、アナログ シグナル チェーンの設計者向けの非常に包括的なオンライン クラスです。インターフェイス シリーズでは、産業用や車載などの多様なアプリケーションで一般的に使用されているプロトコルに関するテクニカル トレーニングを提示します。このトレーニング シリーズでは、ドライバ / レシーバ、バッファ、SerDes、マルチドロップ LVDS、マルチポイント LVDS など、さまざまな LVDS アーキテクチャについて説明します。また、LVDS を使用して設計する際の主な注意事項についても説明します。

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      講演者

      [THEME MUSIC]

      Hello and welcome to TI Precision Labs. In this series, we're going to discuss Low Voltage Differential Signaling or LVDS for short. In this first session, we'll go over the fundamentals of LVDS-- what it is, how it works, and where it can be used. This will include the architecture, electrical characteristics, and application use cases. In future sessions, we will discuss variants of LVDS like multidrop LVDS and multipoint LVDS.

      LVDS can be used in many ways depending on the system needs. There's the typical redriver/receiver pair. But there are also transceivers for full duplex and half duplex communication and buffers for simply buffering the LVDS signals. Since LVDS can be used virtually any time there's a need to transport a signal from one point to another, LVDS applications are ubiquitous, which makes it a popular interface.

      LVDS stands for Low Voltage Differential Signaling and is defined by TIA/EIA-644 standard. It is a physical layer only, which means that it is purely electrical with no protocol for transferring data. We can see this by simply observing its architecture.

      Its most basic form consists of a differential transmitter and differential receiver. Instead of measuring the difference between the signal and ground, like with single-ended signaling, LVDS measures the difference between the non-inverting and inverting levels of the signals.

      A termination resistor is placed at the end of the transmission line to terminate the signal. This termination resistor as well as the LVDS driver current is what generates differential voltage. This resistor must match the characteristic impedance of the transmission line. Typically, it'll be 100 ohms.

      The resistor creates a stub in the transmission line, which can cause reflections. So the resistors should be placed as close to the receiver as possible to minimize the stub length. The signals are also centered around the common-mode voltage of 1.2 volts offset from the ground.

      1.2 volts is typical for 2.5-volt, 3.3-volt 5-volt powered devices. However, other unofficial standards, like sub-LVDS, use the smaller offset voltage of 0.9 volts as they are powered off of a 1.8-volt supply.

      AC coupling can be used to isolate drivers and receivers that require different common-mode voltages. Speaking of AC coupling, if you've watched our previous TI PL video on display port, then this architecture should look familiar to you. Display port's physical layer is just AC coupled LVDS.

      The source is the driver, and the sink is the receiver. One key difference between standard LVDS and display port is that display port is double-terminated with termination on both the source and the sink instead of just the sink. This is only a requirement for the DP standard and is not something you would typically see in other AC-coupled LVDS interfaces. There are other TI PL videos that go into more details about this interface. Links to these videos are provided at the end of the presentation.

      Now, let's take a deeper look into the inner workings of LVDS. The driver has a 3.5 milliamp push-pull mode current source. And each line in the differential pair carries the 3.5 milliamps in opposite directions.

      The output driver sets the common-mode voltage for the DC signals, and the receiver input is very high impedance. So virtually, all the current flows through the 100-ohm termination resistor. This, in turn, is what generates the differential voltage of 350 millivolts across the receiver inputs.

      A compliant receiver is specified to tolerate a minimum of plus or minus 1 volt of ground shift between driver ground and receiver ground. Since a typical driver is specified to have a common-mode voltage of 1.2 volts, this means the receiver will have a common-mode range of 0.2 volts to 2.2 volts. So if the driver and the receiver on different boards with different power supplies, the receiver will still be able to receive signals from the driver even with differences in ground potential.

      Additionally, the receiver is guaranteed to have a receiver threshold of 100 millivolts or less. The typical driver will have a differential voltage of 350 millivolts, which allows for almost 6 dB in losses caused by PCB traces or cables.

      One major benefit of LVDS is noise immunity. Since the lanes are tightly coupled together, noise that appears on one lane will likely also be present on the other lane. This noise is canceled out since the receiver only responds to the differences between the two signals.

      Because of the low-voltage nature of LVDS, another benefit is the low power. We can see this by taking a look at some quick calculations with some typical specifications from an LVDS driver datasheet. The power dissipated is 1.225 milliwatts. The input power is 23.1 milliwatts. And the power consumption is 10.325 milliwatts. Combining these, the total device power is only 33.425 milliwatts.

      Now, one of the most frequently asked questions is just how far and how fast can LVDS go? Typically, the bandwidth is a little more than one gigabits per second at 10 to 15 meters of distance with no signal conditioning. Unfortunately, this is very much a system-dependent parameter, so we can only give typical specs for these parameters.

      The best way to determine what the actual max speed and max distance is is to measure them in the system either through simulation or with a prototype system. For example, a typical setup will include a BERT or function generator, EVMs, various length cables, and an oscilloscope.

      With the prototype setup, you can take eye diagram measurements at the load to determine the max amount of jitter allowed for error-free transmission. You can also use the eye diagram height to determine whether or not the 100 millivolt threshold for the receiver is being met.

      For a recap of eye diagrams, a link to previous TI PL videos is provided at the end of the presentation. Be sure to visit our E2E support forums at TI.com/E2E where we can help answer questions about designing with interface technologies. Please also reference the previous TI PL videos like our videos on display port and eye diagrams.

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      すべて折り畳む
      Develop basic understanding of LVDS ICs. (2)
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      プレシジョン ラボ シリーズ:LVDS

      すべて折り畳む
      Develop basic understanding of LVDS ICs. (2)