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Design Rule Verification Report

Date : 9/4/2014
Time : 12:01:49 PM
Elapsed Time : 00:00:11
Filename : D:\New folder\DP_Ethernet Brick PHY_FINAL\DP_Ethernet Brick PHY_FINAL\ISE3009.PcbDoc
Warnings : 0
Rule Violations : 22

Summary

Warnings Count
Total 0

Rule Violations Count
Differential Pairs Uncoupled Length using the Gap Constraints (Min=16mil) (Max=16mil) (Preferred=16mil) (InDifferentialPair ('TD')) 0
Width Constraint (Min=7mil) (Max=7mil) (Preferred=7mil) (InDifferentialPair('TD')) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=16mil) (Max=16mil) (Preferred=16mil) (InDifferentialPair ('RD')) 0
Width Constraint (Min=7mil) (Max=7mil) (Preferred=7mil) (InDifferentialPair('RD')) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=16mil) (Max=16mil) (Preferred=16mil) (InDifferentialPair ('D3 AND D4')) 1
Width Constraint (Min=7mil) (Max=7mil) (Preferred=7mil) (InDifferentialPair('D3 AND D4')) 0
Net Antennae (Tolerance=0mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Hole Size Constraint (Min=8mil) (Max=251mil) (All) 0
Minimum Annular Ring (Minimum=7mil) (All) 0
Minimum Annular Ring (Minimum=5.905mil) (IsVia and InAnyComponent) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Routing Via (MinHoleWidth=12mil) (MaxHoleWidth=20mil) (PreferredHoleWidth=16mil) (MinWidth=26mil) (MaxWidth=40mil) (PreferedWidth=32mil) (All) 0
Routing Via (MinHoleWidth=12mil) (MaxHoleWidth=20mil) (PreferredHoleWidth=16mil) (MinWidth=26mil) (MaxWidth=40mil) (PreferedWidth=32mil) (IsVia and InAnyComponent) 0
Power Plane Connect Rule(Relief Connect )(Expansion=15mil) (Conductor Width=15mil) (Air Gap=12mil) (Entries=4) (All) 0
Width Constraint (Min=8mil) (Max=100mil) (Preferred=8mil) (All) 0
Clearance Constraint (Gap=8mil) (All),(All) 0
Clearance Constraint (Gap=12mil) (InPolygon),(All) 0
Clearance Constraint (Gap=25mil) (OnCopper and InPoly),(IsKeepOut) 0
Clearance Constraint (Gap=25mil) (InPolygon),(InPolygon) 0
Clearance Constraint (Gap=9mil) (IsVia),(IsSMTPin) 18
Clearance Constraint (Gap=12mil) (IsVia),(IsVia) 0
Clearance Constraint (Gap=7.9mil) (InPadClass('U5')),(InPadClass('U5')) 0
Clearance Constraint (Gap=12mil) (IsVia),(IsThruPin) 0
Clearance Constraint (Gap=40mil) (InPadClass('MTG')),(InPolygon) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=10mil) (Max=10mil) (Preferred=10mil) (All) 0
Width Constraint (Min=7mil) (Max=7mil) (Preferred=7mil) (InDifferentialPair('D2 AND D1')) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=16mil) (Max=16mil) (Preferred=16mil) (InDifferentialPair ('D2 AND D1')) 0
Clearance Constraint (Gap=11mil) (InNetClass('CLK_Signals')),(IsTrack) 3
Total 22


Differential Pairs Uncoupled Length using the Gap Constraints (Min=16mil) (Max=16mil) (Preferred=16mil) (InDifferentialPair ('D3 AND D4'))
Differential Pairs Routing Between Net RX+_RJ45 And Net RX-_RJ45
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Clearance Constraint (Gap=9mil) (IsVia),(IsSMTPin)
Via (1028.819mil,1816.634mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (1028.819mil,1911.122mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (1028.819mil,1958.366mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (1123.307mil,1816.634mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (1123.307mil,1911.122mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (1123.307mil,1958.366mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (1170.551mil,1816.634mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (1170.551mil,1911.122mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (1170.551mil,1958.366mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (1028.819mil,1863.878mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (1123.307mil,1863.878mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (1170.551mil,1863.878mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (1076.063mil,1816.634mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (1076.063mil,1911.122mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (1076.063mil,1958.366mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (1076.063mil,1863.878mil) Top Layer to Bottom Layer Pad U15-41(1099.445mil,1887.5mil) Top Layer
Via (248mil,1032mil) Top Layer to Bottom Layer Pad U4-21(290mil,1016.85mil) Top Layer
Via (330mil,1002mil) Top Layer to Bottom Layer Pad U4-21(290mil,1016.85mil) Top Layer
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Clearance Constraint (Gap=11mil) (InNetClass('CLK_Signals')),(IsTrack)
Track (980.591mil,1976.083mil)(980.591mil,1999.409mil) Top Layer Pad U15-2(980.591mil,1956.398mil) Top Layer
Track (1218.78mil,1838.287mil)(1235.115mil,1838.287mil) Top Layer Pad U15-24(1218.78mil,1857.972mil) Top Layer
Track (1218.78mil,1877.658mil)(1275.342mil,1877.658mil) Top Layer Pad U15-24(1218.78mil,1857.972mil) Top Layer
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