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Design Rule Verification Report

Date : 10/14/2015
Time : 4:48:47 PM
Elapsed Time : 00:00:00
Filename : C:\1 Helen TI work\3 TI reference design,app and training\1.3 TPS61088 reference design PMP9774\1.2 PMP9774 layout Vin supply\PMP9774.PcbDoc
Warnings : 0
Rule Violations : 4

Summary

Warnings Count
Total 0

Rule Violations Count
Net Antennae (Tolerance=0mil) (All) 0
Silk to Silk (Clearance=5mil) (All),(All) 4
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Clearance Constraint (Gap=40mil) (OnCopper and InComponentClass('Mounting Holes')),(IsKeepOut) 0
Clearance Constraint (Gap=20mil) (OnCopper and InPoly),(IsKeepOut) 0
Clearance Constraint (Gap=75mil) (Disabled)(All),(IsKeepOut) 0
Clearance Constraint (Gap=7mil) (All),(All) 0
Clearance Constraint (Gap=20mil) (InPolygon),(All) 0
Total 4

Silk to Silk (Clearance=5mil) (All),(All)
Text "TP5" (2660mil,1230mil) Top Overlay Arc (2715mil,1150mil) Top Overlay
Text "R16" (1906.378mil,1738.64mil) Top Overlay Track (1874mil,1735.84mil)(1899.982mil,1735.84mil) Top Overlay
Text "C19" (1910mil,1693.64mil) Top Overlay Track (1899.982mil,1681.374mil)(1899.982mil,1735.84mil) Top Overlay
Text "R16" (1906.378mil,1738.64mil) Top Overlay Track (1899.982mil,1681.374mil)(1899.982mil,1735.84mil) Top Overlay
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