Altium

Design Rule Verification Report

Date: 8.9.2016
Time: 11:28:09
Elapsed Time: 00:00:05
Filename: C:\Users\a0415314\Desktop\proj\chargepumps\LM27762-Northstar+\TI_Design\LM27762_TI_Design_PCB.PcbDoc
Warnings: 0
Rule Violations: 25

Summary

Warnings Count
Total 0

Rule Violations Count
Board Clearance Constraint (Gap=0mil) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800)) 1
Board Clearance Constraint (Gap=0mil) (OnCopper and InPoly) 0
Board Clearance Constraint (Gap=0mil) (OnCopper and InComponentClass('Mounting Holes')) 0
Net Antennae (Tolerance=0mil) (All) 0
Silk to Silk (Clearance=4mil) (All),(All) 0
Silk to Silk (Clearance=0mil) ((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))),((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))) 0
Silk To Solder Mask (Clearance=4mil) (All),(All) 19
Silk To Solder Mask (Clearance=5mil) (IsPad and InAnycomponent),(All) 0
Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All) 3
Minimum Solder Mask Sliver (Gap=0.7mil) (InComponentClass('Logo')),(InComponentClass('Logo')) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=10mil) (Max=100mil) (Prefered=10mil) and Width Constraints (Min=15mil) (Max=15mil) (Prefered=15mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Pads and Vias to follow the Drill pairs settings 0
Hole Size Constraint (Min=7.874mil) (Max=251mil) (All) 0
Component Clearance Constraint ( Horizontal Gap = 30mil, Vertical Gap = 10mil ) (All),(All) 0
Component Clearance Constraint ( Horizontal Gap = 30mil, Vertical Gap = 30mil ) (IsThruComponent),(IsThruComponent) 0
Component Clearance Constraint ( Horizontal Gap = 40mil, Vertical Gap = 30mil ) (IsThruComponent),(IsSMTComponent) 0
Component Clearance Constraint ( Horizontal Gap = 14.961mil, Vertical Gap = 10mil ) (HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*')),(HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*')) 0
Component Clearance Constraint ( Horizontal Gap = 250mil, Vertical Gap = Infinite ) (InComponentClass('Mounting Holes')),(All) 0
Component Clearance Constraint ( Horizontal Gap = 5mil, Vertical Gap = 10mil ) ((HasFootprint('NY PMS 440 0025 PH'))),((HasFootprint('Keystone_1902C'))) 0
Component Clearance Constraint ( Horizontal Gap = 50mil, Vertical Gap = 10mil ) (InComponentClass('Logo')),(All) 0
Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 0mil ) (InComponentClass('Header')),(InComponentClass('Shunt')) 0
Component Clearance Constraint ( Horizontal Gap = 50mil, Vertical Gap = 10mil ) (InComponentClass('Mounting Holes')),(InComponentClass('FiducialMark')) 0
Acute Angle Constraint (Minimum=45.000) (All) 0
Minimum Annular Ring (Minimum=8mil) (All) 1
Minimum Annular Ring (Minimum=5.905mil) (IsVia and InAnyComponent) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=40mil) (PreferredHoleWidth=16mil) (MinWidth=26mil) (MaxWidth=65mil) (PreferedWidth=34mil) (All) 1
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=12.992mil) (PreferredHoleWidth=7.874mil) (MinWidth=19.685mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (IsVia and InAnyComponent) 0
Routing Layers(All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Width Constraint (Min=6mil) (Max=100mil) (Preferred=10mil) (All) 0
Clearance Constraint (Gap=7.874mil) (All),(All) 0
Clearance Constraint (Gap=25mil) (InPolygon),(All) 0
Clearance Constraint (Gap=0mil) (((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut),(((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut) 0
Total 25

Board Clearance Constraint (Gap=0mil) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800))
Board Outline Clearance(Outline Edge): (71.654mil < 75mil) Between Pad J5-1(114.961mil,1324.331mil) on Top Layer And Board Edge

Back to top

Silk To Solder Mask (Clearance=4mil) (All),(All)
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Arc (3670mil,1110mil) on Bottom Overlay And Via (3620mil,1360mil) from Top Layer to Bottom Layer [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Text "R7" (1900mil,2400mil) on Top Overlay And Via (1880mil,2490mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (0.68mil < 4mil) Between Track (1784mil,2162.8mil)(1809.982mil,2162.8mil) on Top Overlay And Via (1780mil,2140mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0.68mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (1784mil,2297.266mil)(1809.982mil,2297.266mil) on Top Overlay And Via (1780mil,2310mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (3.743mil < 4mil) Between Text "U1" (1836.5mil,2327.5mil) on Top Overlay And Via (1810mil,2350mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [3.743mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (2157.402mil,2212.4mil)(2158.1mil,2213.098mil) on Top Overlay And Via (2170mil,2200mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (3.563mil < 4mil) Between Track (2148.1mil,2160mil)(2148.1mil,2197.6mil) on Top Overlay And Via (2170mil,2200mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [3.563mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (2158.1mil,2213.098mil)(2158.1mil,2250mil) on Top Overlay And Via (2170mil,2200mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (3.932mil < 4mil) Between Track (2192.4mil,2131.9mil)(2192.4mil,2207.402mil) on Top Overlay And Via (2170mil,2200mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [3.932mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (2081.9mil,2212.4mil)(2157.402mil,2212.4mil) on Top Overlay And Via (2170mil,2200mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (3.563mil < 4mil) Between Track (2072.598mil,2197.6mil)(2148.1mil,2197.6mil) on Top Overlay And Via (2170mil,2200mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [3.563mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (2010.018mil,2952.8mil)(2010.018mil,3007.266mil) on Top Overlay And Via (1990mil,2970mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (1976.929mil,2955.433mil)(1976.929mil,2961.339mil) on Top Overlay And Via (1990mil,2970mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (1992.734mil,2924mil)(1992.734mil,2949.982mil) on Top Overlay And Via (1990mil,2970mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (1992.734mil,2949.982mil)(2047.2mil,2949.982mil) on Top Overlay And Via (1990mil,2970mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (3.924mil < 4mil) Between Track (2010.018mil,2952.8mil)(2036mil,2952.8mil) on Top Overlay And Via (1990mil,2970mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [3.924mil]
Silk To Solder Mask Clearance Constraint: (0.332mil < 4mil) Between Track (1854mil,3057.2mil)(1879.982mil,3057.2mil) on Top Overlay And Via (1860mil,3080mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0.332mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (1692.734mil,3059.982mil)(1747.2mil,3059.982mil) on Top Overlay And Via (1720mil,3080mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (1843.071mil,2955.433mil)(1843.071mil,2961.339mil) on Top Overlay And Via (1840mil,2980mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]

Back to top

Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.222mil < 3.937mil) Between Via (1840mil,2980mil) from Top Layer to Bottom Layer And Pad U2-12(1860.787mil,2957.402mil) on Top Layer [Top Solder] Mask Sliver [0.222mil]
Minimum Solder Mask Sliver Constraint: (0.362mil < 3.937mil) Between Via (1780mil,2310mil) from Top Layer to Bottom Layer And Pad C4-2(1781.496mil,2270mil) on Top Layer [Top Solder] Mask Sliver [0.362mil]
Minimum Solder Mask Sliver Constraint: (3.22mil < 3.937mil) Between Via (1880mil,2920mil) from Top Layer to Bottom Layer And Via (1910mil,2920mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [3.22mil] / [Bottom Solder] Mask Sliver [3.22mil]

Back to top

Minimum Annular Ring (Minimum=8mil) (All)
Minimum Annular Ring: (5.905mil < 8mil) Via (1940mil,2920mil) from Top Layer to Bottom Layer (Annular Ring=5.905mil) On (Top Layer)

Back to top

Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=40mil) (PreferredHoleWidth=16mil) (MinWidth=26mil) (MaxWidth=65mil) (PreferedWidth=34mil) (All)
Routing Via Style: Via (1940mil,2920mil) from Top Layer to Bottom Layer Actual Size : 19.685mil Actual Hole Size : 7.874mil

Back to top