비디오 시리즈
Precision labs 시리즈: 클록 및 타이밍 소개
이 비디오 시리즈는 각 제품의 아키텍처, 기능 및 특징에 대한 높은 수준의 논의와 함께 클록 및 타이밍 제품 유형에 대한 개요를 제공합니다. 오실레이터, 클록 버퍼, 지터 클리너, PLL, 네트워크 싱크로나이저에 대한 주요 성능 메트릭에 대해 집중적으로 다루며 주요 매개 변수 및 사양을 중점적으로 설명합니다. 개별 시스템 요구 사항을 충족하는 데 가장 적합한 제품 기능을 설명하기 위해 여러 클록 트리 구성 요소 간의 애플리케이션 사례 예 및 장단점을 제시합니다.
Clocks and timing systems overview
발표자
리소스
Hello and welcome to the TI Precision Labs. What does it mean when you hear the term clock and timing system? It can mean a lot of things. But how does one know which clock I see is the best fit?
This introductory training module provides an overview of the application for different clock and timing functions. The Phase-Lock Loop and VCO functions shown in red are core building blocks used in a variety of the clocking solutions. These PLL and VCO functions and key performance parameters are discussed in additional Precision Labs training modules.
What are clocks? Clocks provide the pulse in electronic systems. In the signal chain, clocks are a key building block that provides reference sample timing to the ADC, DAC, processor, and any interface media.
Clocks are needed in any system that requires a reference time for synchronization, command execution, and data transfer. They provide the frequency inputs to the various devices, allowing them to perform their intended functions. Clocks can also refer to the functional block that multiplies and divides a source to fanout a specific frequency, or even several disparate frequencies. If in your system you require a processor, a high-speed interface, or a data converter, then a clock solution is needed.
We'll start with the most common function, the crystal oscillator. The key parameters are oscillating frequency and accuracy, measured in PPM, and signal quality, measured by jitter or phase noise. The simplified circuit for crystal input is shown in the figure. A crystal is connected across an inverter input and output, where R sub S is a series resistor used to reduce the drive level if needed.
The active circuit inside the chip generates a positive feedback loop, otherwise known as negative resistance, providing a stimulus in order for the crystal to start and maintain oscillation. Due to the high mechanical resonance or q of the crystal, only a specific frequency is allowed to oscillate, depending on the cut of the crystal. Typically, this will be in the frequency range less than 100 megahertz, with most common fundamental resonances less than 40 meg or so. The loading capacitance, CL1 and CL2, are used to control the initial frequency accuracy of the crystal. The output type can be single ended or differential.
Different flavors of reference oscillators infer accuracy and stability. The TCXO is temperature compensated to have a low PPM across an extended temperature range. The OCXO includes an oven or heater to maintain a temperature and have even lower PPM across temperature.
You can also add a voltage control to adjust the load, the capacitance, and frequency in a VCXO or a VCTCXO. A voltage controlled oscillator is similar in some ways to a VCXO. But usually a VCO has much higher frequency and a much wider tuning range. Both the reference oscillator and VCO are components of phase-lock loops. And each contribute to the overall PLL noise.
Real time clocks, or RTC, are everywhere in almost any electronic system. You can think of this as a low power implementation of the crystal oscillator on the previous slide. The trick is to reduce current as much as possible without sacrificing too much frequency accuracy. RTC is commonly run at 32 kilohertz with power consumption in the microamp range, but may only have less PPM accuracy. That's measured in seconds per day.
Timers are used in many applications, but most commonly for battery operated circuitry, especially when a backup battery source needs an extended life. No one likes to unexpectedly find a dead battery. For a timer, you add some logic to the internal oscillator, and a counter will count down the milliseconds or minutes.
Once the counter is empty and the timer expires, a wake-up signal is provided. This technique allows shutting off the entire system and waking up the controller after a few minutes or hours to perform housekeeping tasks or start normal operation. The sleep current can be dramatically reduced to the nanoamp range.
Sleep time is very important in watchdog timers as it also affects current consumption for the entire system. If your system has processors, high-speed I/O, communication or physical layer connectivity, there will be several clock frequencies required to support these processing and communication networks. There are also IC clocking solutions with higher levels of integration to provide similar functions at a lower build materials cost and an increased reliability.
When there is a need for multiple copies of a single frequency, such as four times at 25 megahertz or maybe you need eight signals which are of 100 megahertz clock frequencies, then a clock buffer may be a better fit than multiple XOs. A clock buffer, also referred to as a fanout, takes an input and fans out copies of the input frequency to multiple outputs. A clock buffer can typically have 1 to n, where n is 2 outputs, up to 1 to 12 or even 1 to 20.
In a simple fanout buffer, usually you're looking for a very low jitter or low solution cost and low output to output skew. Similar to crystal oscillators, there are differential and single ended output types, along with other options that can be included for flexibility and performance. In universal buffers, as in differential formats, higher performance is expected.
And a specification such as propagation delay and possibly delay variation, in addition to the skew in an additive jitter, can be important. You also need a way for configuring the functionality, such as I2C, spy, or pin control, to select your desired input/output types and your I/O voltage levels to interface with the system needs. Typical formats supported would be LVCMOS, LVDS, and LVPECL, HCSL, among others.
Now it is often the case that a system will need more than a simple fanout buffer to support multiple frequencies. For example, what do you do if you need 25 megahertz, 100 megahertz, and 156.25 megahertz? A clock generator is a special kind of circuit that produces multiple frequency outputs from a single reference input through one or more phase-lock loops. The clock generator takes a stimulus or a reference input, which can be a crystal, an oscillator, or a clock output from a previous stage in the clock tree, and from this, generates multiple frequencies or multiple copies of the same frequency as required.
A phase-lock loop or a PLL is a feedback system where the VCO tracks the phase and frequency of the reference input. As a result, the VCO output frequency is the phase detector frequency multiplied in times. For more details on PLL and VCO building blocks, visit Precision Labs phase-lock loop fundamentals training series.
Each output divider D in a clock generator can select one of the PLLs, divide it down, and generate an output frequency. Sometimes multiple outputs are grouped together and share a common output divider. In that case, these outputs will always have the same clock frequency.
Why is a clock generator needed? When a system use case, such as networking and factory automation, or maybe medical imaging, requires disparate clock frequencies, a clock generator is more suitable than using multiple oscillators and/or crystals. For the purpose of future discussion, the output buffers dividers will be referred to as the clock distribution block.
Looking at clocking operation in a different way, you can divide into three main analog clock architectures. Shown here is a simplified block diagram showing the reference at a clock distribution network. The clock distribution or clock buffer does not filter any noise. It can only add jitter. But it is simple and low power.
The single loop, common in clock generators, does both jitter cleaning and frequency multiplication in the same step. The single loop does provide some filtering of the reference for a higher frequency noise greater than 10 kilohertz because of the PLL VCO operation. However, the dual or cascaded loop will do a better job cleaning jitter at frequency offsets closer to the carrier because it will use a VCXO crystal oscillator in the first jitter cleaning PLL.
The first PLL, PLL1, should have a narrow loop bandwidth to filter out noise for the reference. The second PLL, PLL2, should have a wide loop bandwidth to take advantage of the jitter cleaned reference. The second PLL performs more of a frequency multiplication function to allow the distribution block to divide down to the desired output frequencies. A dual cascaded loop architecture would be used in the case of a noisy reference input, for example, if you wanted to use a recovered [INAUDIBLE] clock as your input reference clock, or if you needed low phase noise close into the carrier, since a typical VCO does not have good close-in phase noise performance less than 10 kilohertz.
When the input and output frequency have a poor integer relationship, you may also want to use a jitter cleaner. For example, if you have a 12.288 megahertz reference compared to a 2.5 gigahertz VCO, this would result in a very low 32 kilohertz phase detector frequency. A higher phase detector comparison frequency will generally improve the PLL performance. A dual loop could provide a 10 megahertz or 100 megahertz reference input to the second PLL, which is a factor of more than 300, or 3,000 times comparison frequency.
Synchronization is required for multiple frequency sources, providing a deterministic phase relationship between input and multiple frequency outputs. Often jitter cleaners will include delay compensation networks in the distribution paths to help balance out any routing differences between the outputs. Synchronization, in fact, is becoming more and more important for time-critical applications. And to address this function, a network synchronizer is a key component that is often used to address some of the more challenging ITU and telecom standards.
Many ITU, telecom, and 4G, 5G standards dictate time and frequency synchronization to be guaranteed at all times. A network synchronizer provides a highly stable clock at all times, irrespective of the presence of a reference input or not. Redundant inputs are monitored and switched over, based on qualification and on priority, in a hitless manner, with very low phase disturbance.
The Digital Phase-Lock Loop, or DPLL, provides a holdover function on loss of reference and can be programmed to loop bandwidths of less than 1 hertz. Imagine the size of a capacitor you'd need to achieve this sub-1 hertz bandwidth in the analog domain. The frequency output tracks the stability of the reference close-in. And the DPLL bandwidth dictates the long-term aspect of wander and phase transient.
And the XO and the APLL dictate the short-term clock aspect, phase noise and spurious. Mixed signal techniques are used for best performance. However, the on-chip LCVCO often poses some limitations. A new architecture, integrating Bulk Acoustic Wave, or a BAW oscillator, to the network synchronizer, takes the best aspects of DPLL and APLL and combines them together, resulting in a decrease of in-band noise. Typically, only a low frequency XO is sufficient to achieve jitter of less than 100 femtoseconds.
That concludes this introductory video on clocks and timing. Thank you for watching. Please test your knowledge of the material with a simple five-question quiz to wrap up. If you need more information or technical resources on TI clocks and timing products, please visit ti.com and type in /clocks.
Let's check your answers. Number one is false. A clock generator, jitter cleaner, or a network synchronizer can provide multiple frequency domains from a single reference. The second one is true. All of these functions may be included in a clock distribution block with at least one output buffer always present.
Number three is false. Since a clock buffer replicates the input, there is no frequency error introduced. The skew measures the phase difference between the outputs.
The fourth is true. The PLL1 has a narrow loop bandwidth to filter out noise from the reference. And the PLL2 performs a frequency multiplication to allow the distribution block to divide down to the desired output frequencies.
And then the last one is also not correct. A network synchronizer maintains a time and frequency accuracy, whether switching between references or going into holdover mode with no references present. So it's pretty immune to whether or not the reference is stable or goes in and out.