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Precision labs 시리즈: 클록 및 타이밍 시스템의 잡음

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      발표자

      Hello and welcome to the TI Precision Labs series on Noise in Clock and Timing Systems. Adhering to a clock jitter budget is often one of the most critical parts of a system design. In this module, we will explore the definitions and types of jitter, as well as some of these system level impairments caused by excessive jitter or phase noise.

      Clock jitter is a short term fluctuation, or variation of the clock edges, with respect to the clock's expected or ideal location. Any source, like periodic, aperiodic, or data-dependent sources, can cause clock edges to deviate from their ideal positions. Common sources of these variations include internal device noise, such as thermal noise, flicker noise, et cetera, imperfections in clock generation circuitry, power supply noise, board level imperfections, like crosstalk, data-dependent interference, reflections due to poor terminations, and other board-level causes, system level imperfections, such as electromagnetic interference susceptibility. Clock jitter can generally be classified into two primary groups-- unbounded or random jitter and bounded or deterministic jitter.

      Unbounded, or random, jitter is caused by stochastic or Gaussian processes in every system. Instantaneous values of this noise source is unbounded, and it is inherent to every system. Deterministic jitter is caused by non-stochastic processes, and this is not inherent to every system. Deterministic jitter can be periodic, like noise from a DC/DC switcher or data-dependent, like intersymbol interference. Data-dependent deterministic jitter can also be non-correlated as well as correlated. While random jitter is difficult to eliminate, deterministic data can be reduced by careful system design.

      While bounded jitter is expressed as peak-to-peak jitter, unbounded jitter is expressed as RMS jitter. Peak-to-peak jitter is defined as the difference between the minimum deviation and maximum deviation of the clock edge. When jitter is calculated for different sample lengths, 10,000 samples according to JEDEC standard, the histogram follows a normal or Gaussian distribution. RMS jitter is the value of one standard deviation sigma of that histogram. Peak-to-peak jitter is the distance between the largest and smallest measurement on the histogram plot.

      Since random jitter is unbounded, a maximum bit error rate is needed to convert RMS jitter into peak-to-peak jitter. BER, or Bit Error Rate, is defined as the number of erroneous bits in the unit time interval. For example, a BER of 10 to the minus 12 indicates a maximum error of one bit in 10 to the 12 cycles. To convert RMS jitter into peak-to-peak jitter, a BER multiplier is used based on the assumption of a Gaussian noise model. For a BER of 10 to the minus 12, peak-to-peak jitter is equal to 14.069 times the RMS jitter. For other BERs, peak-to-peak jitter can be calculated from RMS jitter based on the multipliers shown in the table here.

      In serial data communication, data is transferred from the transmitter to the receiver through a link or physical medium. In some cases, the clock can be transferred through a different link. The speed and efficiency of data transmission depends upon many electrical and physical factors. One of the factors includes clock jitter. If clock jitter is too high, data cannot be recovered at the receiver end. In order to evaluate the performance of the serial link, a data-dependent electrical measurement is used to evaluate high speed data quality and high speed transmitter-receiver performance.

      Eye diagrams are a good generic tool that can be used when designing and simulating systems, evaluating products with high speed links. In order to generate the eye diagram, incoming data is repeatedly sampled and persistently displayed on an oscilloscope. If the data link is bad or noisy, the eye would close, and there would be high error in the data transmission. When the link is good, the eye diagram would show a clear opening of the eye.

      The eye diagram can be observed on the reference clock with respect to an ideal clock with zero mean frequency error. The jitter of the reference clock can also be observed in this eye diagram. There are also several key horizontal measurements that can be made with an eye diagram. Eye width is the most important of these measurements and allows you to understand how much time the receiver has to sample a bit within one unit interval.

      This measurement is normally taken at the widest part of the eye, or the crossover region. Achieving a specific eye width is critical in passing an eye diagram test, and the limitations of the eye opening are normally described in an eye mask. The eye width also gives a sense of how open the eye diagram is from a timing perspective. Total jitter can be measured for the eye diagram and decomposed into its fundamental components by the oscilloscope.

      As total jitter increases, the available eye width of your signal decreases and affects how the receiver samples the transmitted data. The eye opening can also be used to extract an estimate for bit error rate for the specific eye diagram. Systems with large amounts of total jitter tend to have poor signal performance and probably suffer from high bit error rate due to smaller eye opening and may not pass an eye mask. However, by introducing a high speed signal conditioner, the amount of jitter in the system can be reduced and some eye width can be recovered helping to pass the eye mask test, achieve acceptable signal quality performance, increase the eye opening, and decrease the overall bit error rate.

      The edge rate can also be extracted from the eye diagram and can be useful in determining specific effects that may cause a shift of the crossover region, affecting the eye width and different loading effects of the transmission line. The edge rate can also be another parameter tested for in eye diagrams when implementing some high speed data protocols to ensure proper transmitter performance. Depending on the specification, the edge rate can be measured in slightly different ways, such as a 90%/10%, an 80/20%, or a 70/30% voltage levels. In the diagram shown here, the measured points are at the 90/10% voltage levels.

      An Analog to Digital Converter, or ADC, is used to convert any analog quantity, for example voltage recurrent, into a digital word. In an ideal scenario, the digital word should be an exact representation of the analog value being measured. Since a clock source is used to sample the incoming analog quantity, the noise in the clock source introduces noise in the sampled value.

      Assuming a band-limited signal at the input of a sinusoidal nature, the slope of the signal is going to be dependent upon the sinusoidal frequency. The jitter in the clock source is multiplied by the slope of the incoming signal and converts into noise at the sampler, in this case voltage noise. The higher the clock source jitter, the higher is the noise at the sampler. The higher the slope of the input signal, the higher the noise at the sampler.

      Jitter in the clock source will limit the maximum input frequency at a particular signal-to-noise ratio. This figure here shows a representative plot of the achievable signal to noise ratio in an ADC with various clock sources. Effective SNR is given in the formula, where sigma is the peak-to-peak clock jitter.

      This concludes this training module on jitter. Look for the series on Noise in Clock and Timing Systems to be continued in TI Precision Labs. Please try our short five-question quiz to check your understanding of this video's content. To find more technical information and to search for products, please visit TI.com/clocks.

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      Precision labs 시리즈: 클록 및 타이밍 시스템의 잡음