비디오 시리즈
Precision Labs 시리즈: USB
USB IC로 설계하는 방법을 알아보세요.
USB 설계를 위한 레이아웃 기본 사항
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Hello, and welcome to TI Precision Labs. In this series, we're going to discuss layout basics for Universal Serial Bus, or USB. USB is the world's most popular and widely-used computer interface. It is used in consumer, industrial, and automotive applications, both simple and complex.
Layout of USB designs is not complicated, but to preserve signal quality, several factors need to be considered. In this session, we will cover the most common layout topics for USB signals, impedance, trace length and matching, and printed circuit board, or PCB stack-up. The examples in the session focus on USB 2.0 high speed, but apply to both USB 3.0 Gen 1 and Gen 2 designs as well.
In USB, signals are transmitted using differential signaling. USB 2.0 uses a single differential pair of signals, DP and DM. The USB 3.0 specification adds super-speed signaling using two additional sets of differential pairs, SSTX and SSRX, to support a separate, full-duplex connection. Please note that the USB 3.0 specification is cumulative, so references to the USB 3.2 spec will apply to the Legacy 5G USB 3.0-type connections as well.
The USB 2.0 specification defines a differential characteristic impedance of 90 ohms, plus or minus 15%, for the USB 2.0 differential pair. The USB 3.0 specification defines a differential characteristic impedance range of 72 ohms to 120 ohms. To optimize signal quality, this differential impedance should be maintained across the entire USB path from the transmitter through the PCB traces to the connector and cable, and over to the next connector, PCB traces, and receiver. Impedance discontinuities can result in signal reflections and degrade signal quality.
Since the majority of USB PCB applications we review route the differential signals on the external PCB layers, we will focus on micro-strip impedance calculations. Differential and single-ended impedance are calculated using the equations shown on the left. If the differential signals are routed on internal PCB layers, then the impedance formulas for strip-line applications must be used. The equations have been simplified using a dielectric constant of 4.4 for the FR-4 PCB material. 4.1 to 4.5 is the typical range used for the dielectric constant of FR-4.
In these equations, w is the trace width, t is the trace thickness, d the trace separation between the differential pair, and h is the dielectric thickness. Differential impedance, Z Diff, is less than twice the single-ended impedance, Z naught. The differential impedance depends greatly upon trace spacing in micro-strip applications. The smaller the differential pair spacing, the lower the differential impedance.
Impedance can have a noticeable impact on signal quality. We can analyze the signal quality by using an eye diagram. Please see the TI Precision Labs video on diagrams for more information on how eye diagrams are generated. On the left is an eye diagram from a 90-ohm differential source, passing through a 90-ohm differential layout, terminating in a 90-ohm differential load. On the right is an eye diagram for a 90-ohm differential impedance source, passing through a 100-ohm differential layout, and terminating in a 90-ohm differential load. The impact from the reflections can be seen as the closing of the left side of the eye. A longer section of mismatch layout would result in impact to the entire eye.
Like all high-speed signals, USB trace lengths should be minimized to reduce channel loss and prevent noise. A general recommendation is to keep USB traces to eight inches or less, so that the signal quality at the connector is not degraded. 10G USB trace lengths would need to be even shorter. Long PCB traces require very careful routing, and USB redrivers are often recommended. More information on redrivers and signal conditioners can be found in the Interface section of TI Precision Labs.
In addition to minimizing trace lengths, the individual traces of each differential pair should be matched in length to each other, within 150 mils for USB 2.0 and five mils for USB 3.0, to prevent noise and preserve the differential signaling. Less mismatches are always better. The trace lengths of the SSTX pair and the SSRX pair do not need to match each other. In addition, the super-speed pairs can be polarity f to ease routing.
When matching the routing links of the USB signals, it is possible to add serpentine routing to match the links, as shown here. Serpentine routing should be grouped with any other discontinuities in the trace routing or at the connector. Mismatched signals will have a slightly different timing due to propagation delay. A rule of thumb for propagation delay in PCBs is 165 picoseconds per inch.
The exact formula for micro-strip propagation delay is shown here, and yields a value slightly lower, about 140 picoseconds per inch. This equals about 20 to 25 picoseconds for 150 mils of mismatch, which is negligible for USB 2.0 signals, which have a unit interval of 2.08 nanoseconds, and eight picoseconds for five mils of mismatch for USB 3.0 signals, which have a UI of 200 picoseconds for Gen 1. For faster signals, internal bond wire mismatches may also need to be taken into account. In the table shown, the mismatch must be taken to account for USB 3.0 5G signals but is inconsequential for USB 2.0 signals.
Looking at the impact of trace length, on the left is an eye diagram from a very short trace layout of two inches. On the right is an eye diagram for a layout with a longer trace length of 10 inches. You can see there is a decrease in eye opening and some impact to eye height. This shows how trace length may affect the opening of a high-speed signal.
Trace length matching can also have an impact on signal quality. On the left, again, is an eye diagram from a match length layout, less than 50 mils mismatch. On the right, is an eye diagram for a layout with a trace length mismatch of 1.5 inches. The eye width is impacted.
The impact of trace length matching on signal quality can be difficult to see in a USB 2.0 eye, so we created an exaggerated mismatch. On the left is an eye diagram from a matched length layout, less than 50 mils mismatch. On the right is an eye diagram for a layout with a trace length gross mismatch of seven inches. Noticeably noisier signaling, an impact to the width can be seen.
PCB stack-up also has an impact on USB signal quality. Because of the high frequencies associated with USB, a PCB stack-up with at least four layers is recommended to provide a solid ground plane under the differential pairs. An ideal stack-up, typically used on EVMs, is shown on the left, with two signal layers separated by a ground layer and a power layer. Routing priority should be given to the high-speed signal traces, placing them on the top layer, above the solid ground plane, or, when necessary, on the bottom layer, taking care not to route at right angles, over power plane splits.
If a circuit is complex and signals must be routed on inner layers as strip-line traces, care should be taken to separate signal layers with ground layers or with power layers. A sample motherboard stack-up is shown on the right, with all signal layers isolated by ground layers. If layer-to-layer trace routing is required, the number of vias should be minimized. Differential pair vias should be symmetric and have accompanying ground vias to maintain ground return path.
Here's an example of a non-ideal PCB stack and how it impacts signal quality. On the left is an eye diagram from a PCB stack-up, with the differential pair routed over a solid ground plane. On the right is an eye diagram for a two-layer PCB, without a solid ground plane reference, using only ground fills near the differential pairs.
In conclusion, paying attention to impedance, trace length, and PCB stack-up can help preserve signal quality, dropping the bit error rate, and preventing USB packet drops that can impact system throughput.
To recap what we discussed, let's go over a short quiz.
True or false, the spacing between the two signals of a differential pair impacts the differential characteristic impedance.
True. The spacing between two signals of a differential pair affects the differential characteristic impedance, especially in micro-strip applications.
True or false, as long as the traces of a differential pair are matched in length, the total length has no impact on signal quality.
False. The longer the trace, the more the signal will be attenuated. This causes the vertical eye opening to be reduced in the eye diagram.
True or false the traces of a differential pair must be perfectly matched in length.
False. There is some tolerance within the USB spec that allows for mismatch in a differential pair of a high-speed signal.
True or false, high-speed differential pairs should be routed over a solid ground plane when possible.
True. Routing priority should be given to the high-speed signal traces, placing them on the top layer, above the solid ground plane, or, when necessary, on the bottom layer, taking care not to route at right angles over power plane splits.
So that wraps up this discussion about USB layout basics. You can get more information about the latest USB technology and solutions from TI in our TI E2E community. Go to TI.com/e2e for answers to many helpful questions and for other information. Thanks.