Design Name C:/Users/a0274226/Documents/MyDocs/Projects/LAUNCHXL-CC1312R1/Rev-D/Cadence/LAUNCHXL-CC1312R1.brd
Date Wed Oct 10 11:13:46 2018
DRC Error Count Summary
DRC Error Type DRC Error Count
Package to Package 31
Route Keepin 12
Route Keepout 1
Manufacturing Constraint 6
Miscellaneous 63
Total DRC Errors 113

Detailed DRC Errors
Constraint Name DRC Marker Location Required Value Actual Value Constraint Source Constraint Source Type Element 1 Element 2 Comment
Package to Package Spacing (227.9600 258.3800) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M10 Package Geometry/Place_Bound_Top" Shape "M9 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (206.1000 288.1156) 0 MM 10 MM NONE DESIGN Shape "M17 Package Geometry/Place_Bound_Bottom" Shape "P8 Package Geometry/Place_Bound_Bottom"  
Package to Package Spacing (240.5833 207.4640) 2.8 MM 3.81 MM PACKAGE_HEIGHT_MIN DESIGN Shape "J7 Package Geometry/Place_Bound_Top" Filled Rectangle "Ti_Logo_1 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (233.0600 255.0780) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M12 Package Geometry/Place_Bound_Top" Shape "M11 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (222.8600 255.0780) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M8 Package Geometry/Place_Bound_Top" Shape "M7 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (222.8600 253.3000) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M8 Package Geometry/Place_Bound_Top" Shape "M7 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (215.2600 255.0780) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M5 Package Geometry/Place_Bound_Top" Shape "M4 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (227.9600 255.0780) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M10 Package Geometry/Place_Bound_Top" Shape "M9 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (233.0600 258.3800) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M12 Package Geometry/Place_Bound_Top" Shape "M11 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (233.0600 253.3000) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M12 Package Geometry/Place_Bound_Top" Shape "M11 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (215.2600 258.3800) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M5 Package Geometry/Place_Bound_Top" Shape "M4 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (215.2600 253.3000) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M5 Package Geometry/Place_Bound_Top" Shape "M4 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (222.8600 258.3800) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M8 Package Geometry/Place_Bound_Top" Shape "M7 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (227.9600 253.3000) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M10 Package Geometry/Place_Bound_Top" Shape "M9 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (217.7600 253.3000) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M5 Package Geometry/Place_Bound_Top" Shape "M6 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (217.7600 255.0780) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M6 Package Geometry/Place_Bound_Top" Shape "M5 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (217.7600 258.3800) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M6 Package Geometry/Place_Bound_Top" Shape "M5 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (203.4418 176.7356) 0 MM 10 MM NONE DESIGN Shape "M15 Package Geometry/Place_Bound_Bottom" Shape "Mh1 Package Geometry/Place_Bound_Bottom"  
Package to Package Spacing (201.3544 181.9107) 0 MM 10 MM NONE DESIGN Shape "M15 Package Geometry/Place_Bound_Bottom" Shape "Fidu5 Package Geometry/Place_Bound_Bottom"  
Package to Package Spacing (216.8850 218.5000) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M2 Package Geometry/Place_Bound_Top" Shape "M1 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (257.7624 178.8861) 0 MM 10 MM NONE DESIGN Shape "M16 Package Geometry/Place_Bound_Bottom" Shape "Mh2 Package Geometry/Place_Bound_Bottom"  
Package to Package Spacing (255.1473 183.3471) 0 MM 10 MM NONE DESIGN Shape "M16 Package Geometry/Place_Bound_Bottom" Shape "Fidu6 Package Geometry/Place_Bound_Bottom"  
Package to Package Spacing (216.8850 220.2780) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M2 Package Geometry/Place_Bound_Top" Shape "M1 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (200.9312 291.4595) 0 MM 10 MM NONE DESIGN Shape "M17 Package Geometry/Place_Bound_Bottom" Shape "Mh3 Package Geometry/Place_Bound_Bottom"  
Package to Package Spacing (201.5086 290.9630) 0 MM 0.2 MM NONE DESIGN Shape "Mh3 Package Geometry/Place_Bound_Bottom" Shape "P8 Package Geometry/Place_Bound_Bottom"  
Package to Package Spacing (216.8850 223.5800) 3.81 MM 9.91 MM PACKAGE_HEIGHT_MIN DESIGN Shape "M2 Package Geometry/Place_Bound_Top" Shape "M1 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (254.6057 294.3043) 0 MM 10 MM NONE DESIGN Shape "M18 Package Geometry/Place_Bound_Bottom" Shape "Mh4 Package Geometry/Place_Bound_Bottom"  
Package to Package Spacing (239.8000 207.4640) 0 MM 2.8 MM NONE DESIGN Shape "J7 Package Geometry/Place_Bound_Top" Filled Rectangle "Ti_Logo_1 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (221.9570 223.2030) 0 MM 0.4 MM NONE DESIGN Shape "R7 Package Geometry/Place_Bound_Top" Shape "R5 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (218.4880 228.2620) 0 MM 0.4 MM NONE DESIGN Shape "R8 Package Geometry/Place_Bound_Top" Shape "R9 Package Geometry/Place_Bound_Top"  
Package to Package Spacing (229.1120 208.6880) 0 MM 0.6 MM NONE DESIGN Shape "C37 Package Geometry/Place_Bound_Top" Shape "C36 Package Geometry/Place_Bound_Top"  
Shape to Route Keepin Spacing (214.7000 291.5000) 0 MM 0 MM DEFAULT NET SPACING CONSTRAINTS Shape(auto-generated) "N1031635 Etch/L2" Shape "Route Keepin/All"  
Shape to Route Keepin Spacing (216.3000 293.6000) 0 MM 0 MM DEFAULT NET SPACING CONSTRAINTS Shape(auto-generated) "Gnd Etch/L2" Shape "Route Keepin/All"  
Shape to Route Keepin Spacing (201.4910 247.3390) 0 MM 0 MM DEFAULT NET SPACING CONSTRAINTS Shape(auto-generated) "Gnd Etch/Top" Shape "Route Keepin/All"  
Shape to Route Keepin Spacing (206.5000 293.6000) 0 MM 0 MM DEFAULT NET SPACING CONSTRAINTS Shape(auto-generated) "Gnd Etch/Top" Shape "Route Keepin/All"  
Shape to Route Keepin Spacing (216.3000 293.6000) 0 MM 0 MM DEFAULT NET SPACING CONSTRAINTS Shape(auto-generated) "Gnd Etch/Bottom" Shape "Route Keepin/All"  
Shape to Route Keepin Spacing (214.7000 291.5000) 0 MM 0 MM DEFAULT NET SPACING CONSTRAINTS Shape(auto-generated) "N1031635 Etch/Bottom" Shape "Route Keepin/All"  
Shape to Route Keepin Spacing (258.0000 244.5000) 0 MM 0 MM DEFAULT NET SPACING CONSTRAINTS Shape(auto-generated) "Gnd Etch/L3" Shape "Route Keepin/All"  
Shape to Route Keepin Spacing (255.8213 251.2814) 0 MM 0 MM DEFAULT NET SPACING CONSTRAINTS Shape "Route Keepin/All" Shape(auto-generated) "Gnd Etch/L3"  
Shape to Route Keepin Spacing (201.4620 294.8000) 0 MM 0 MM DEFAULT NET SPACING CONSTRAINTS Shape(auto-generated) "Gnd Etch/Top" Shape "Route Keepin/All"  
Shape to Route Keepin Spacing (202.6929 250.5264) 0 MM 0 MM DEFAULT NET SPACING CONSTRAINTS Shape(auto-generated) "Gnd Etch/Top" Shape "Route Keepin/All"  
Shape to Route Keepin Spacing (206.4848 294.8000) 0 MM 0 MM DEFAULT NET SPACING CONSTRAINTS Shape(auto-generated) "Gnd Etch/Top" Shape "Route Keepin/All"  
Shape to Route Keepin Spacing (257.0380 294.8000) 0 MM 0 MM DEFAULT NET SPACING CONSTRAINTS Shape(auto-generated) "Gnd Etch/Top" Shape "Route Keepin/All"  
Shape to Route Keepout Spacing (246.1460 187.3000) 0 MM 0 MM DEFAULT NET SPACING CONSTRAINTS Shape "N2245591 Etch/Top" Shape "Route Keepout/Top"  
Pad Soldermask to Pad Soldermask Spacing (218.4500 228.2240) 0.001 MM 0 MM SOLDERMASK_SPACING DESIGN Pin "R8.2 (Dio30/Tcxo_Vcc)" Pin "R9.1 (Dio30/Tcxo_Vcc)"  
Pad Soldermask to Pad Soldermask Spacing (221.9000 223.2000) 0.001 MM 0 MM SOLDERMASK_SPACING DESIGN Pin "R5.1 (N2239551)" Pin "R7.2 (N2239551)"  
Pad Soldermask to Pad Soldermask Spacing (218.4500 228.2500) 0.001 MM 0 MM SOLDERMASK_SPACING DESIGN Pin "R9.1 (Dio30/Tcxo_Vcc)" Pin "R8.2 (Dio30/Tcxo_Vcc)"  
Pad Soldermask to Pad Soldermask Spacing (221.9034 223.2034) 0.001 MM 0 MM SOLDERMASK_SPACING DESIGN Pin "R7.2 (N2239551)" Pin "R5.1 (N2239551)"  
Symbol Soldermask to Pad Soldermask Spacing (200.5003 257.6007) 0.001 MM 0 MM SOLDERMASK_SPACING DESIGN Shape "Package Geometry/Soldermask_Top" Pin "Mh5.1 (Gnd)"  
Symbol Soldermask to Pad Soldermask Spacing (200.5001 257.6009) 0.001 MM 0 MM SOLDERMASK_SPACING DESIGN Shape "Package Geometry/Soldermask_Bottom" Pin "Mh5.1 (Gnd)"  
Via at SMD fit (244.6500 217.4500) TRUE FALSE NONE DESIGN Via "Via_04Cir02 (244.0000 217.4500) (Gnd)" Pin "U4.9 (Gnd)"  
Via at SMD fit (244.6500 217.4500) TRUE FALSE NONE DESIGN Via "Via_04Cir02 (245.3000 217.4500) (Gnd)" Pin "U4.9 (Gnd)"  
Via at SMD thru (209.9000 283.8500) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (209.0500 283.0000) (Gnd)" Pin "U15.33 (Gnd)"  
Via at SMD thru (209.9000 283.8500) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (210.9000 283.0250) (Gnd)" Pin "U15.33 (Gnd)"  
Via at SMD thru (209.9000 283.8500) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (209.9000 283.8500) (Gnd)" Pin "U15.33 (Gnd)"  
Via at SMD thru (254.7300 263.8000) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (253.6400 263.3000) (Gnd)" Pin "U33.11 (Gnd)"  
Via at SMD thru (244.6500 217.4500) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (245.3000 217.4500) (Gnd)" Pin "U4.9 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (231.4250 227.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (230.4250 227.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (230.4250 228.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (229.4250 228.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (228.4250 228.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (227.4250 228.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (231.4250 229.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (230.4250 229.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (229.4250 229.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (225.3500 284.2250) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (227.1000 283.5500) (Gnd)" Pin "U7.9 (Gnd)"  
Via at SMD thru (254.7300 263.8000) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (253.1000 262.5500) (Gnd)" Pin "U33.11 (Gnd)"  
Via at SMD thru (254.7300 263.8000) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (254.2000 264.4000) (Gnd)" Pin "U33.11 (Gnd)"  
Via at SMD thru (254.7300 263.8000) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (254.0800 262.5500) (Gnd)" Pin "U33.11 (Gnd)"  
Via at SMD thru (244.6500 217.4500) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (244.0000 217.4500) (Gnd)" Pin "U4.9 (Gnd)"  
Via at SMD thru (217.0500 287.7500) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (217.0500 287.2000) (Gnd)" Pin "U47.9 (Gnd)"  
Via at SMD thru (231.8500 263.0800) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (232.7600 263.6000) (Gnd)" Pin "U38.11 (Gnd)"  
Via at SMD thru (231.8500 263.0800) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (232.7200 262.5500) (Gnd)" Pin "U38.11 (Gnd)"  
Via at SMD thru (231.8500 263.0800) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (231.8400 263.1000) (Gnd)" Pin "U38.11 (Gnd)"  
Via at SMD thru (231.8500 263.0800) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (231.2800 263.6000) (Gnd)" Pin "U38.11 (Gnd)"  
Via at SMD thru (231.8500 263.0800) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (231.2800 262.5000) (Gnd)" Pin "U38.11 (Gnd)"  
Via at SMD thru (233.4500 275.9750) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (232.9500 276.9000) (Gnd)" Pin "U42.9 (Gnd)"  
Via at SMD thru (233.4500 275.9750) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (234.0000 276.9000) (Gnd)" Pin "U42.9 (Gnd)"  
Via at SMD thru (233.4500 275.9750) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (232.9500 275.0000) (Gnd)" Pin "U42.9 (Gnd)"  
Via at SMD thru (233.4500 275.9750) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (234.0000 275.0000) (Gnd)" Pin "U42.9 (Gnd)"  
Via at SMD thru (233.4500 275.9750) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (233.4500 275.9500) (Gnd)" Pin "U42.9 (Gnd)"  
Via at SMD thru (231.9750 289.6500) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (231.0000 290.1500) (Gnd)" Pin "U46.9 (Gnd)"  
Via at SMD thru (231.9750 289.6500) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (232.9500 290.2000) (Gnd)" Pin "U46.9 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (230.4250 226.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (231.9750 289.6500) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (232.9500 289.1000) (Gnd)" Pin "U46.9 (Gnd)"  
Via at SMD thru (231.9750 289.6500) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (231.9500 290.2000) (Gnd)" Pin "U46.9 (Gnd)"  
Via at SMD thru (231.9750 289.6500) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (232.0000 289.1000) (Gnd)" Pin "U46.9 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (229.4250 227.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (228.4250 227.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (231.4250 226.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (227.4250 227.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (229.4250 226.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (217.0500 287.7500) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (217.0500 288.2500) (Gnd)" Pin "U47.9 (Gnd)"  
Via at SMD thru (225.3500 284.2250) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (227.1000 282.5000) (Gnd)" Pin "U7.9 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (228.4250 226.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (231.4250 228.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (227.4250 230.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (228.4250 229.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (228.4250 230.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (229.4250 230.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (230.4250 230.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (231.4250 230.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (226.1750 283.0000) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (226.1500 282.5000) (Gnd)" Pin "U7.9 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (227.4250 226.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (209.9000 283.8500) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (208.7000 285.0000) (Gnd)" Pin "U15.33 (Gnd)"  
Via at SMD thru (229.4750 228.2000) FALSE TRUE NONE DESIGN Via "Via_Chip (227.4250 229.1500) (Gnd)" Pin "U1.49 (Gnd)"  
Via at SMD thru (209.9000 283.8500) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (210.9500 284.9000) (Gnd)" Pin "U15.33 (Gnd)"  
Via at SMD thru (225.3500 284.2250) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (225.2500 283.5500) (Gnd)" Pin "U7.9 (Gnd)"  
Via at SMD thru (225.3500 284.2250) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (226.2000 283.5500) (Gnd)" Pin "U7.9 (Gnd)"  
Via at SMD thru (225.3500 284.2250) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (225.2500 282.4500) (Gnd)" Pin "U7.9 (Gnd)"  
Via at SMD thru (254.7300 263.8000) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (253.1500 264.3500) (Gnd)" Pin "U33.11 (Gnd)"  
Via at SMD thru (231.9750 289.6500) FALSE TRUE NONE DESIGN Via "Via_04Cir02 (231.0000 289.1000) (Gnd)" Pin "U46.9 (Gnd)"