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Design Rule Verification Report

Date : 9/23/2014
Time : 12:28:33 PM
Elapsed Time : 00:04:48
Filename : D:\TIDA-00222\Design Files - TIDA-00222\TIDA-00222.PcbDoc
Warnings : 0
Rule Violations : 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=7.8mil) ((InPadClass('All Pads'))),(All) 0
Clearance Constraint (Gap=5mil) (IsVia),(IsPad) 0
Clearance Constraint (Gap=20mil) (InPolygon),(InPolygon) 0
Clearance Constraint (Gap=8mil) (IsVia),(IsVia) 0
Width Constraint (Min=8mil) (Max=100mil) (Preferred=20mil) (InNetClass('PWR')) 0
Routing Via (MinHoleWidth=16mil) (MaxHoleWidth=20mil) (PreferredHoleWidth=16mil) (MinWidth=30mil) (MaxWidth=40mil) (PreferedWidth=30mil) (InNetClass('PWR')) 0
Minimum Annular Ring (Minimum=5mil) (IsVia and InAnyComponent) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=12.992mil) (PreferredHoleWidth=7.874mil) (MinWidth=19.685mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (InNet('GND_SIGNAL')) 0
Acute Angle Constraint (Minimum=45.000) (All) 0
Net Antennae (Tolerance=0mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Hole Size Constraint (Min=7.8mil) (Max=251mil) (All) 0
Minimum Annular Ring (Minimum=5mil) (All) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Routing Via (MinHoleWidth=12mil) (MaxHoleWidth=20mil) (PreferredHoleWidth=12mil) (MinWidth=24mil) (MaxWidth=40mil) (PreferedWidth=24mil) (All) 0
Routing Layers(All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Width Constraint (Min=8mil) (Max=100mil) (Preferred=10mil) (All) 0
Clearance Constraint (Gap=33mil) (OnCopper and InComponentClass('Mounting Holes')),(IsKeepOut) 0
Clearance Constraint (Gap=8mil) (All),(All) 0
Clearance Constraint (Gap=20mil) (InPolygon),(All) 0
Clearance Constraint (Gap=8mil) (IsVia),(IsPad) 0
Total 0