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Design Rule Verification Report

Date : 3/23/2015
Time : 1:53:27 PM
Elapsed Time : 00:00:01
Filename : D:\Project Files\TIDA-00440DB1\Design Files\20150323\TIDA-00440DB\TIDA-00440DB.PcbDoc
Warnings : 0
Rule Violations : 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0.178mm) ((InPadClass('Less than 9 Mil Clearance'))),((InPadClass('All Pads'))) 0
Clearance Constraint (Gap=0.381mm) (InPolygon),(InPolygon) 0
Clearance Constraint (Gap=0.203mm) (All),(All) 0
Width Constraint (Min=0.203mm) (Max=2.54mm) (Preferred=0.203mm) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.254mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Routing Layers(All) 0
Routing Via (MinHoleWidth=0.305mm) (MaxHoleWidth=0.508mm) (PreferredHoleWidth=0.305mm) (MinWidth=0.66mm) (MaxWidth=1.016mm) (PreferedWidth=0.66mm) (All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Minimum Annular Ring (Minimum=0.15mm) (IsVia and InAnyComponent) 0
Minimum Annular Ring (Minimum=0.15mm) (All) 0
Hole Size Constraint (Min=0.203mm) (Max=6.375mm) (All) 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
Clearance Constraint (Gap=0.203mm) (IsVia),(IsVia) 0
Clearance Constraint (Gap=0.203mm) (IsVia),(IsSMTPin) 0
Clearance Constraint (Gap=0.381mm) (InPolygon),(All) 0
Total 0