Altium

Design Rule Verification Report

Date: 10/14/2016
Time: 10:57:52 AM
Elapsed Time: 00:00:03
Filename: \\FTCODEPOT\appsupport\BoardLayout\Altium\TIDA-00725\TIDA-00725_TIA_OPA857_THS4541_AltiumDesignFiles\TIA_OPA857_THS4541-A.PcbDoc
Warnings: 1
Rule Violations: 0

Summary

Warnings Count
Your board contains 1 shelved polygon - copper connectivity will not be reported correctly. Unshelve polygons and re-run DRC check before producing manufacturing outputs. 1
Total 1

Rule Violations Count
Component Clearance Constraint ( Horizontal Gap = 1.586mil, Vertical Gap = 1.586mil ) ((InComponent('C19') OR InComponent('U6'))),(All) 0
Component Clearance Constraint ( Horizontal Gap = 10mil, Vertical Gap = 10mil ) ((InComponent('H3') OR InComponent('H4') OR InComponent('VOCM') OR InComponent('OUT+'))),((InComponent('H3') OR InComponent('H4') OR InComponent('VOCM') OR InComponent('OUT+'))) 0
Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 0mil ) ((InComponent('H2') OR InComponent('H6'))),(All) 0
Component Clearance Constraint ( Horizontal Gap = 10mil, Vertical Gap = 0mil ) ((InComponent('H2') OR InComponent('+5V'))),(All) 0
Minimum Solder Mask Sliver (Gap=3.338mil) ((InComponent('C24') OR InComponent('C25') OR IsVia)),(All) 0
Minimum Solder Mask Sliver (Gap=3.339mil) ((InComponent('U2') OR InComponent('U7'))),(All) 0
Clearance Constraint (Gap=10mil) (InNamedPolygon('Bottom Layer-GND')),(All) 0
Clearance Constraint (Gap=9.843mil) (InNamedPolygon('Bottom Layer L4-NetL2-1')),(All) 0
Clearance Constraint (Gap=10mil) (InNamedPolygon('Bottom Layer L4-VAMP_5P0')),(All) 0
Clearance Constraint (Gap=9.483mil) (InNamedPolygon('Top Layer L1-NetL2-1')),(All) 0
Clearance Constraint (Gap=10mil) (InNamedPolygon('Top Layer L1-NetL2-1')),(All) 0
Clearance Constraint (Gap=10mil) (InNamedPolygon('Top Layer L1-NetL2-1')),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Silk to Silk (Clearance=0mil) (All),(All) 0
Silk to Silk (Clearance=0mil) ((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))),((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))) 0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All) 0
Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.7mil) (InComponentClass('Logo')),(InComponentClass('Logo')) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=10mil) (Max=100mil) (Prefered=10mil) and Width Constraints (Min=15mil) (Max=15mil) (Prefered=15mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Pads and Vias to follow the Drill pairs settings 0
Hole Size Constraint (Min=7.874mil) (Max=251mil) (All) 0
Component Clearance Constraint ( Horizontal Gap = 30mil, Vertical Gap = 10mil ) (All),(All) 0
Component Clearance Constraint ( Horizontal Gap = 40mil, Vertical Gap = 30mil ) (IsThruComponent),(IsThruComponent) 0
Component Clearance Constraint ( Horizontal Gap = 10mil, Vertical Gap = 30mil ) (IsThruComponent),(IsSMTComponent) 0
Component Clearance Constraint ( Horizontal Gap = 7mil, Vertical Gap = 0mil ) (HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*') or HasFootprint('YFF0012AFAF*') or HasFootprint('TRANS_NexFET_Q5B*') or HasFootprint('TO-5 (3 PIN) - (100 mil) SM*') or HasFootprint('QFN 3.15X3.15 (16PIN)*') or HasFootprint('RGT0016A*') or HasFootprint('DDC0005A*')),(HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*') or HasFootprint('YFF0012AFAF*') or HasFootprint('TRANS_NexFET_Q5B*') or HasFootprint('TO-5 (3 PIN) - (100 mil) SM*') or HasFootprint('QFN 3.15X3.15 (16PIN)*') or HasFootprint('RGT0016A*') or HasFootprint('DDC0005A*')) 0
Component Clearance Constraint ( Horizontal Gap = 250mil, Vertical Gap = Infinite ) (InComponentClass('Mounting Holes')),(All) 0
Component Clearance Constraint ( Horizontal Gap = 5mil, Vertical Gap = 10mil ) ((HasFootprint('NY PMS 440 0025 PH'))),((HasFootprint('Keystone_1902C'))) 0
Component Clearance Constraint ( Horizontal Gap = 50mil, Vertical Gap = 10mil ) (InComponentClass('Logo')),(All) 0
Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 0mil ) (InComponentClass('Header')),(InComponentClass('Shunt')) 0
Component Clearance Constraint ( Horizontal Gap = 50mil, Vertical Gap = 10mil ) (InComponentClass('Mounting Holes')),(InComponentClass('FiducialMark')) 0
Minimum Annular Ring (Minimum=5.905mil) (All) 0
Minimum Annular Ring (Minimum=5.905mil) (IsVia and InAnyComponent) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=40mil) (PreferredHoleWidth=16mil) (MinWidth=19.685mil) (MaxWidth=65mil) (PreferedWidth=34mil) (All) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=12.992mil) (PreferredHoleWidth=7.874mil) (MinWidth=19.685mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (IsVia and InAnyComponent) 0
Routing Layers(All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=35mil) (Air Gap=10mil) (Entries=4) (All) 0
Clearance Constraint (Gap=7.874mil) (All),(All) 0
Clearance Constraint (Gap=25mil) (InPolygon),(All) 0
Clearance Constraint (Gap=75mil) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and Not IsKeepout),(IsKeepOut) 0
Clearance Constraint (Gap=25mil) (OnCopper and InPoly),(IsKeepOut) 0
Clearance Constraint (Gap=40mil) (OnCopper and InComponentClass('Mounting Holes')),(IsKeepOut) 0
Clearance Constraint (Gap=10mil) (((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut),(((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut) 0
Clearance Constraint (Gap=10mil) (InNamedPolygon('Top Layer L1-V3P3_1')),(All) 0
Clearance Constraint (Gap=10mil) (InNamedPolygon('Top Layer L1-GND')),(All) 0
Clearance Constraint (Gap=10mil) (InNamedPolygon('Top Layer L1-5VIN')),(All) 0
Clearance Constraint (Gap=10mil) (InNamedPolygon('Bottom Layer L4-5VIN')),(All) 0
Clearance Constraint (Gap=10mil) (InNamedPolygon('Bottom Layer L4-NetC5_1')),(All) 0
Clearance Constraint (Gap=6.693mil) (InComponent('U2')),(All) 0
Total 0

Warnings

Your board contains 1 shelved polygon - copper connectivity will not be reported correctly. Unshelve polygons and re-run DRC check before producing manufacturing outputs.
Polygon named: GND Layer L2-No Net In net GND

Back to top