Hello, and welcome to The Logic Minute. In this video, the second installment of the LSF family series, we will explain how the bias circuit works for an LSF device. Shown on the right is a typical application schematic with an LSF device translating signals between two external devices operating at different voltage nodes. The bias circuit is located at the top of the schematic and contains the following components.

The A-side supply, which is commonly referred to as VccA or the low-side supply, which must be at least 0.8 volts less than VccB. The B-side supply, which is commonly referred to as VccB, or the high-side supply, a 200 kiloohm resistor, a 0.1 microfarad capacitor. While not a component, the voltage node at VREF B and the EN, or Enable Pin, is very important to proper operation of the device.

A very common design error with the LSF 01 series of device is to attempt to drive the enable pin directly with a push/pull output device. We will cover how to properly use the enable pin in a different video.

Note that the last three items on the list are integrated into the LSF 02 series of devices and do not need to be added externally. To really understand how the bias circuit works, we have to look inside the LSF. LSF translators use four port and channel FETs to carry out the translation, shown here circled in blue.

Each channel has its own FET, and all the gates are tied together directly, shown here in red. The enable pin is connected to the gates of all channels, including the reference FET. The enable and VREF B pins are externally shorted and the entire VREF B voltage node, shown in red, provides the gate voltage for not only the two FETs shown, but the FETs on every channel of the device.

The 0.1 microfarad capacitor connected to the VREF B voltage node provides a path to ground for high frequency noise. While it is not required for operation, it is highly recommended.

The reference FET is diode connected, meaning that as long as the voltage from VREF B to VREF A is larger than the FET's threshold value, current will conduct from B to A. The 200 kiloohm resistor limits the current through the reference FET to just a few microamps, which will flow from supply B through the reference FET and into supply A, as indicated by the red arrows.

It is very important to note that current will be flowing into the A-side supply during normal operation, and not all voltage sources can sync current. So be sure that your design can handle this current. The current that's being conducted through the reference FET will force a voltage from VREF A to VREF B, which will be the FET's threshold voltage.

Because the VREF B voltage node is connected directly to every gate, the gate voltage can be easily calculated. Using Kirchhoff's Voltage Law, you can find that the gate voltage referenced to ground will be equal to the voltage across the external capacitor, labeled here V bias. The bias voltage turns out to be the A supply value plus the FET's threshold.

This voltage, which we will call the gate bias voltage, or just V bias in the next few videos, is crucial for operation of the LSF family of translators. The bias circuitry can be replaced by a DC supply to simplify analysis. And in future videos, the external bias components will be hidden so that we can focus on how the translation actually works.

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