Home Data converters Analog-to-digital converters (ADCs) High-speed ADCs (≥10 MSPS)
Home
Data converters
Analog-to-digital converters (ADCs)
High-speed ADCs (≥10 MSPS)

ADC10040-Q1

ACTIVE

10-Bit, 40-MSPS Analog-to-Digital Converter (ADC) - Qualified for Automotive Applications

Order now
Data sheet

A newer version of this product is available

open-in-new Compare alternates
Similar functionality to the compared device
NEW ADC3910S065 ACTIVE 10-bit, one-channel, 65-MSPS ADC single clock cycle latency up to 16x decimation digital comparator Higher sampling rate and smaller package size

ADC10040-Q1

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 40 Resolution (bps) 10 Number of input channels 1 Interface type Parallel CMOS, TTL Analog input BW (MHz) 400 Features Low Power Rating Automotive Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 55.5 Architecture Pipeline SNR (dB) 58.7 ENOB (bit) 9.6 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 40 Resolution (bps) 10 Number of input channels 1 Interface type Parallel CMOS, TTL Analog input BW (MHz) 400 Features Low Power Rating Automotive Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 55.5 Architecture Pipeline SNR (dB) 58.7 ENOB (bit) 9.6 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer No
TSSOP (PW) 28 62.08 mm² 9.7 x 6.4
  • Single +3.0V Operation
  • Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 VP-P full-scale input swing
  • 400 MHz −3 dB Input Bandwidth
  • Low Power Consumption
  • Standby Mode
  • On-Chip Reference and Sample-and-Hold Amplifier
  • Offset Binary or Two’s Complement Data Format
  • Separate Adjustable Output Driver Supply to Accommodate 2.5V and 3.3V Logic Families
  • AEC-Q100 Grade 3 Qualified
  • 28-Pin TSSOP Package

Key Specifications

  • Resolution: 10 Bits
  • Conversion Rate: 40 MSPS
  • Full Power Bandwidth: 400 MHz
  • DNL: ±0.3 LSB typ)
  • SNR (fIN = 11 MHz): 59.6 dB (typ)
  • SFDR (fIN = 11 MHz): -80 dB (typ)
  • Power Consumption, 40 MHz: 55.5 mW

All trademarks are the property of their respective owners.

  • Single +3.0V Operation
  • Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 VP-P full-scale input swing
  • 400 MHz −3 dB Input Bandwidth
  • Low Power Consumption
  • Standby Mode
  • On-Chip Reference and Sample-and-Hold Amplifier
  • Offset Binary or Two’s Complement Data Format
  • Separate Adjustable Output Driver Supply to Accommodate 2.5V and 3.3V Logic Families
  • AEC-Q100 Grade 3 Qualified
  • 28-Pin TSSOP Package

Key Specifications

  • Resolution: 10 Bits
  • Conversion Rate: 40 MSPS
  • Full Power Bandwidth: 400 MHz
  • DNL: ±0.3 LSB typ)
  • SNR (fIN = 11 MHz): 59.6 dB (typ)
  • SFDR (fIN = 11 MHz): -80 dB (typ)
  • Power Consumption, 40 MHz: 55.5 mW

All trademarks are the property of their respective owners.

The ADC10040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 55.5 mW at 40 MSPS, including the reference current. The Standby feature reduces power consumption to just 13.5 mW.

The differential inputs provide a full scale selectable input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is user choice of offset binary or two’s complement.

The ADC10040Q runs on an Automotive Grade Flow and is AEC-Q100 Grade 3 Qualified.

This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40°C to +85°C.

The ADC10040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 55.5 mW at 40 MSPS, including the reference current. The Standby feature reduces power consumption to just 13.5 mW.

The differential inputs provide a full scale selectable input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is user choice of offset binary or two’s complement.

The ADC10040Q runs on an Automotive Grade Flow and is AEC-Q100 Grade 3 Qualified.

This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40°C to +85°C.
filter Find other High-speed ADCs (≥10 MSPS)
Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* Data sheet ADC10040/ADC10040Q 10-Bit, 40 MSPS, 3V, 55.5 mW A/D Converter datasheet (Rev. M) 18 Apr 2013
User guide ADC10040/65/80 10-Bit, 40/65/80 MSPS, 3 Volt, 55.5/68.5/78.6 mW ADC User Guide 20 Feb 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 28 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos