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RF-sampling transceivers

AFE7422

ACTIVE

2-transmit, 2-receive RF-sampling transceiver, 10-MHz to 6-GHz, max 1200-MHz IBW

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Data sheet

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AFE7903 ACTIVE 2-transmit, 2-receive RF-sampling transceiver, 5-MHz to 7.4-GHz, max 400-MHz IBW Lower power and increased performance RF-sampling 2T2R

AFE7422

ACTIVE
Data sheet Order now

Product details

Applications General purpose Number of TXs and RXs 2 TX Number of DUCs per TX 2 Number of DDCs per RX 2 RF frequency (max) (MHz) 6000 RF frequency (min) (MHz) 10 Operating temperature range (°C) -40 to 85 Rating Catalog
Applications General purpose Number of TXs and RXs 2 TX Number of DUCs per TX 2 Number of DDCs per RX 2 RF frequency (max) (MHz) 6000 RF frequency (min) (MHz) 10 Operating temperature range (°C) -40 to 85 Rating Catalog
FCBGA (ABJ) 400 289 mm² 17 x 17 FCBGA (ALK) 400 289 mm² 17 x 17
  • Two, 14-bit, 9-GSPS DACs
    • Up to 1200-MHz signal bandwidth
    • 1 DSA per channel tunes output power
  • Two, 14-Bit, 3-GSPS ADCs
    • Up to 1500-MHz signal bandwidth
    • NSD: –151 dBFS/Hz
    • AC performance at fIN = 2.6 GHz, –3 dBFS
      • SNR: 55 dBFS
      • SFDR: 73 dBc HD2 and HD3
      • SFDR: 91 dBc worst spur
    • 2 DSA per channel extends dynamic range
    • RF and digital power detectors
  • RF frequency range: 10 MHz to 6 GHz
  • Fast frequency hopping < 1 µs
  • Receive digital signal path:
    • Bypassable quad DDC per ADC
    • 3-phase coherent 32-bit NCOs per DDC
    • Decimation ratio: 2x to 32x
  • Transmit digital signal path:
    • Quad DUC per DAC with 32-bit NCOs
    • Interpolation ratio: 6x to 36x
    • Sin(x)/x correction and configurable delay
    • Power amplifier protection (PAP)
  • JESD204B interface:
    • 8 transceivers at up to 15 Gbps
    • Subclass 1 multichip synchronization
  • Clocks:
    • Internal PLL and VCO with bypass option
    • Clock output up to 3 GHz with clock divider
  • DAC power dissipation: 1.8 W/ch at 9 GSPS
  • ADC power dissipation: 1.9 W/ch at 3 GSPS
  • Package: 17-mm x 17-mm FC BGA, 0.8-mm pitch
  • Two, 14-bit, 9-GSPS DACs
    • Up to 1200-MHz signal bandwidth
    • 1 DSA per channel tunes output power
  • Two, 14-Bit, 3-GSPS ADCs
    • Up to 1500-MHz signal bandwidth
    • NSD: –151 dBFS/Hz
    • AC performance at fIN = 2.6 GHz, –3 dBFS
      • SNR: 55 dBFS
      • SFDR: 73 dBc HD2 and HD3
      • SFDR: 91 dBc worst spur
    • 2 DSA per channel extends dynamic range
    • RF and digital power detectors
  • RF frequency range: 10 MHz to 6 GHz
  • Fast frequency hopping < 1 µs
  • Receive digital signal path:
    • Bypassable quad DDC per ADC
    • 3-phase coherent 32-bit NCOs per DDC
    • Decimation ratio: 2x to 32x
  • Transmit digital signal path:
    • Quad DUC per DAC with 32-bit NCOs
    • Interpolation ratio: 6x to 36x
    • Sin(x)/x correction and configurable delay
    • Power amplifier protection (PAP)
  • JESD204B interface:
    • 8 transceivers at up to 15 Gbps
    • Subclass 1 multichip synchronization
  • Clocks:
    • Internal PLL and VCO with bypass option
    • Clock output up to 3 GHz with clock divider
  • DAC power dissipation: 1.8 W/ch at 9 GSPS
  • ADC power dissipation: 1.9 W/ch at 3 GSPS
  • Package: 17-mm x 17-mm FC BGA, 0.8-mm pitch

The AFE7422 is a dual-channel, wideband, RF-sampling analog front end (AFE) based on 14-bit, 9-GSPS DACs and 14-bit, 3-GSPS ADCs. With operation at an RF of up to 6 GHz, this device enables direct RF sampling into the C-band frequency range without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multimission systems.

The DAC signal paths support interpolation and digital up conversion options that deliver up to 1200 MHz of signal bandwidth. The differential output path includes a digital step attenuator (DSA), which enables tuning of output power.

Each ADC input path includes a dual DSA and RF and Digital power detectors. Flexible decimation options provide optimization of data bandwidth and a decimation bypass mode is also available for widest signal bandwidth.

An 8-lane (8 TX + 8 RX) subclass-1 compliant JESD204B interface operates at up to 15 Gbps. A bypassable on-chip PLL simplifies clock operation with an optional clock output.

The AFE7422 is a dual-channel, wideband, RF-sampling analog front end (AFE) based on 14-bit, 9-GSPS DACs and 14-bit, 3-GSPS ADCs. With operation at an RF of up to 6 GHz, this device enables direct RF sampling into the C-band frequency range without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multimission systems.

The DAC signal paths support interpolation and digital up conversion options that deliver up to 1200 MHz of signal bandwidth. The differential output path includes a digital step attenuator (DSA), which enables tuning of output power.

Each ADC input path includes a dual DSA and RF and Digital power detectors. Flexible decimation options provide optimization of data bandwidth and a decimation bypass mode is also available for widest signal bandwidth.

An 8-lane (8 TX + 8 RX) subclass-1 compliant JESD204B interface operates at up to 15 Gbps. A bypassable on-chip PLL simplifies clock operation with an optional clock output.
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Technical documentation

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Type Title Date
* Data sheet AFE7422 Dual-channel, RF-sampling AFE with 14-bit, 9-GSPS DACs and 14-bit, 3-GSPS ADCs datasheet (Rev. A) PDF | HTML 25 Jan 2019
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
Application note AFE74xx Power Dissipation Comparison Across Modes 07 Dec 2019
Application note Temp Profile to Maintain Optimum FIT Performance 23 Jul 2019
Technical article How to achieve fast frequency hopping PDF | HTML 03 Mar 2019
Application note AFE74xx as a single-chip wideband repeater using loopback mode PDF | HTML 29 Jan 2019
Application note Evaluating the frequency hopping capability of the AFE74xx PDF | HTML 03 Dec 2018
EVM User's guide AFE7444EVM and AFE7422EVM User's Guide 10 Oct 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
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Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
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Calculation tool

FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator

This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of (...)

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FCBGA (ABJ) 400 Ultra Librarian
FCBGA (ALK) 400 Ultra Librarian
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