The AFE79xx is a family of high performance, wide bandwidth multi-channel transceivers, integrating four RF sampling transmitter chains, four RF sampling receiver chains, and up to two RF sampling digitizing auxiliary chains (feedback paths). The high dynamic range of the transmitter and receiver chains allows the device to generate and receive 3G, 4G, and 5G signals from wireless base stations, while the wide bandwidth capability of the AFE79xx devices is designed for multi-band 4G and 5G base stations.
Each receiver chain includes a 25-dB range DSA (Digital Step Attenuator), followed by a 3-GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. The single or dual digital down converters (DDC) provide up to 600 MHz of combined signal BW. In TDD mode, the receiver channel can be configured to dynamically switch between the traffic receiver (TDD RX) and wideband feedback receiver (TDD FB), with the capability of re-using the same analog input for both purposes.
Each transmitter chain includes a single or dual digital up converters (DUCs) supporting up to 1200-MHz combined signal bandwidth. The output of the DUCs drives a 12-GSPS DAC (digital to analog converter) with a mixed mode output option to enhance 2nd or 3rd Nyquist operation. The DAC output includes a variable gain amplifier (TX DSA) with 40-dB range and 1-dB analog and 0.125-dB digital steps.
The feedback path includes an 25-dB range DSA driving a 3-GSPS RF sampling ADC, followed by a DDC with up to 1200-MHz bandwidth.
See the full data sheet and other design resources for the commercial wireless-specific AFE7988. Request now
For all other applications, see our general-purpose RF-sampling AFEs.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | AFE79xx Quad-Channel RF Transceiver With Feedback Path datasheet (Rev. C) | PDF | HTML | 23 Jun 2020 |
| Application note | RF Sampling Resource Guide | PDF | HTML | 05 Mar 2024 | |
| Application note | AFE79xx Layout Guide (Rev. B) | 06 Apr 2021 | ||
| Application note | System Design Considerations when Upgrading from JESD204B to JESD204C (Rev. A) | 05 Apr 2021 | ||
| Application note | AFE76xx, AFE77xx, and AFE79xx JESD204 Layer Testing | 15 Apr 2020 | ||
| Application note | Temp Profile to Maintain Optimum FIT Performance | 23 Jul 2019 |
For additional terms or required resources, click any title below to view the detail page where available.
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The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| FCBGA (ABJ) | 400 | Ultra Librarian |
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