Home Logic & voltage translation Flip-flops, latches & registers D-type flip-flops
Home
Logic & voltage translation
Flip-flops, latches & registers
D-type flip-flops

CD54HC374

ACTIVE

High Speed CMOS Logic Octal Positive-Edge Triggered D-Type Flip-Flops with 3-State Output

Order now
Data sheet

CD54HC374

ACTIVE
Data sheet Order now

Product details

Number of channels 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 23 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 23 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 20 167.464 mm² 24.2 x 6.92
  • Buffered inputs
  • Common three-state output enable control
  • Three-state outputs
  • Bus line driving capability
  • Typical propagation delay (clock to Q) = 15 ns at VCC = 5 V, CL = 15 pF, TA = 25℃
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: –55℃ to 125℃
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL Logic ICs
  • HC types
    • 2-V to 6-V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types
    • 4.5-V to 5.5-V Operation
    • Direct LSTTL input logic compatibility, VIL = 0.8 V (max), VIH = 2 V (min)
    • CMOS input compatibility, II ≤ 1µA at VOL, VOH
  • Buffered inputs
  • Common three-state output enable control
  • Three-state outputs
  • Bus line driving capability
  • Typical propagation delay (clock to Q) = 15 ns at VCC = 5 V, CL = 15 pF, TA = 25℃
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: –55℃ to 125℃
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL Logic ICs
  • HC types
    • 2-V to 6-V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types
    • 4.5-V to 5.5-V Operation
    • Direct LSTTL input logic compatibility, VIL = 0.8 V (max), VIH = 2 V (min)
    • CMOS input compatibility, II ≤ 1µA at VOL, VOH
filter Find other D-type flip-flops
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Similar functionality to the compared device
NEW SN74LV2T74-EP ACTIVE Enhanced-product dual D-type flip-flops with clear, preset and integrated level shifter Voltage range (1.65V to 5.5V), voltage translation capable

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 15
Type Title Date
* Data sheet CDx4HC374 High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered datasheet (Rev. E) PDF | HTML 14 Oct 2022
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Package Pins CAD symbols, footprints & 3D models
CDIP (J) 20 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos