CD74HCT356

Name: CD74HCT356
Brand: TI
SKU: CD74HCT356
Price: 0.785 USD

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High Speed CMOS Logic 8-Input Multiplexer/Register with 3-State Outputs

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Data sheet

document-pdfAcrobat CD74HCT356 datasheet (Rev. A)

CD74HCT356

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Data sheet

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Product details

Technology family

HCT

Function

Digital Multiplexer

Configuration

8:1

Number of channels

1

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Technology family

HCT

Function

Digital Multiplexer

Configuration

8:1

Number of channels

1

Operating temperature range (°C)

-55 to 125

Rating

Catalog

PDIP (N)

20

228.702 mm² 24.33 x 9.4

Edge-Triggered Data Flip-Flops
- Transparent Select Latches
Buffered Inputs
3-State Complementary Outputs
Bus Line Driving Capability
Typical Propagation Delay: V_CC= 5V, C_L = 15pF, T_A = 25°C
- Clock to Output = 22ns
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
4.5V to 5.5V Operation
Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Edge-Triggered Data Flip-Flops
- Transparent Select Latches
Buffered Inputs
3-State Complementary Outputs
Bus Line Driving Capability
Typical Propagation Delay: V_CC= 5V, C_L = 15pF, T_A = 25°C
- Clock to Output = 22ns
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
4.5V to 5.5V Operation
Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

The CD74HCT356 consists of data selectors/multiplexers that select one of eight sources. The data select bits (S0, S1, and S2) are stored in transparent latches that are enabled by a low latch enable input (LE\).

The data is stored in edge-triggered flip-flops that are triggered by a low-to-high clock transition.

In both types the 3-state outputs are controlled by three output-enable inputs (OE1\, OE2\, and OE3).

The CD74HCT356 consists of data selectors/multiplexers that select one of eight sources. The data select bits (S0, S1, and S2) are stored in transparent latches that are enabled by a low latch enable input (LE\).

The data is stored in edge-triggered flip-flops that are triggered by a low-to-high clock transition.

In both types the 3-state outputs are controlled by three output-enable inputs (OE1\, OE2\, and OE3).

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