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CDC340

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1-to-8 TTL clock driver with output control pins for high state

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Data sheet

CDC340

ACTIVE
Data sheet Order now

Product details

Function Single-ended Output frequency (max) (MHz) 80 Number of outputs 8 Output supply voltage (V) 5 Core supply voltage (V) 5 Output skew (ps) 0.6 Features Pin control Operating temperature range (°C) 0 to 70 Rating Catalog Output type TTL Input type TTL
Function Single-ended Output frequency (max) (MHz) 80 Number of outputs 8 Output supply voltage (V) 5 Core supply voltage (V) 5 Output skew (ps) 0.6 Features Pin control Operating temperature range (°C) 0 to 70 Rating Catalog Output type TTL Input type TTL
SOIC (DW) 20 131.84 mm² 12.8 x 10.3
  • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
  • TTL-Compatible Inputs and Outputs
  • Distributes One Clock Input to Eight Outputs
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • High-Drive Outputs (-48-mA IOH, 48-mA IOL)
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Plastic Small-Outline (DW) and Shrink

    EPIC-IIB is a trademark of Texas Instruments Incorporated.
  • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
  • TTL-Compatible Inputs and Outputs
  • Distributes One Clock Input to Eight Outputs
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • High-Drive Outputs (-48-mA IOH, 48-mA IOL)
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Plastic Small-Outline (DW) and Shrink

    EPIC-IIB is a trademark of Texas Instruments Incorporated.

The CDC340 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a high state regardless of the A input.

The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for customer use and should be strapped to GND.

The CDC340 is characterized for operation from 0°C to 70°C.

The CDC340 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a high state regardless of the A input.

The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for customer use and should be strapped to GND.

The CDC340 is characterized for operation from 0°C to 70°C.

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* Data sheet 1-Line To 8-Line Clock Driver datasheet (Rev. B) 21 May 1997

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