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CDCV857A

NOT RECOMMENDED FOR NEW DESIGNS

2.5-V SSTL-II phase-lock loop clock driver for double data-rate synchronous DRAM applications

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Data sheet

CDCV857A

NOT RECOMMENDED FOR NEW DESIGNS
Data sheet Order now

Product details

Function Zero-delay Core supply voltage (V) 2.5 Output skew (ps) 75 Operating temperature range (°C) 0 to 85 Rating Catalog
Function Zero-delay Core supply voltage (V) 2.5 Output skew (ps) 75 Operating temperature range (°C) 0 to 85 Rating Catalog
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 60 to 180 MHz
  • Low Jitter (cyc–cyc): ±50 ps
  • Distributes One Differential Clock Input to Ten Differential Outputs
  • Three-State Outputs When the Input Differential Clocks Are <20 MHz
  • Operates From Dual 2.5-V Supplies
  • Available in a 48-Pin TSSOP Package or 56-Ball MicroStar Junior™ BGA Package
  • Consumes < 200-uA Quiescent Current
  • External Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks

MicroStar Junior is a trademark of Texas Instruments Incorporated.
  • Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 60 to 180 MHz
  • Low Jitter (cyc–cyc): ±50 ps
  • Distributes One Differential Clock Input to Ten Differential Outputs
  • Three-State Outputs When the Input Differential Clocks Are <20 MHz
  • Operates From Dual 2.5-V Supplies
  • Available in a 48-Pin TSSOP Package or 56-Ball MicroStar Junior™ BGA Package
  • Consumes < 200-uA Quiescent Current
  • External Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks

MicroStar Junior is a trademark of Texas Instruments Incorporated.

The CDCV857A is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]\) and one differential pair of feedback clock output (FBOUT, FBOUT\). The clock outputs are controlled by the clock inputs (CLK, CLK\), the feedback clocks (FBIN, FBIN\), and the analog power input (AVDD). When PWRDWN\ is high, the outputs switch in phase and frequency with CLK. When PWRDWN\ is low, all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power mode). The device also enters this low power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and enables the outputs.

When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857A is also able to track spread spectrum clocking for reduced EMI.

Since the CDCV857A is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV857A is characterized for operation from 0°C to 85°C.

The CDCV857A is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]\) and one differential pair of feedback clock output (FBOUT, FBOUT\). The clock outputs are controlled by the clock inputs (CLK, CLK\), the feedback clocks (FBIN, FBIN\), and the analog power input (AVDD). When PWRDWN\ is high, the outputs switch in phase and frequency with CLK. When PWRDWN\ is low, all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power mode). The device also enters this low power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and enables the outputs.

When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857A is also able to track spread spectrum clocking for reduced EMI.

Since the CDCV857A is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV857A is characterized for operation from 0°C to 85°C.
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* Data sheet 2.5-V Phase Lock Loop Clock Driver datasheet (Rev. A) 11 Sep 2002

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