Packaging information
| Package | Pins NFBGA (ZXS) | 216 |
| Operating temperature range (°C) -40 to 105 |
| Package qty | Carrier 90 | JEDEC TRAY (5+1) |
Features for the DLPC120-Q1
- AEC-Q100
qualified
for automotive
applications:
- Temperature grade 2: –40°C to 105°C ambient
- Compatibility
with
three
DMD
devices:
- DLP3030-Q1: 0.3 WVGA S450
- DLP3020-Q1: 0.3 WVGA S247
- DLP3021-Q1: 0.3 WVGA S247
- Video
input
interface:
- 24-bit parallel (RGB888, RGB666, or RGB565)
- 60-Hz frame rate
- Input resolutions from QVGA through WVGA
- Pixel clock up to 40 MHz
- Video
processing:
- Image scaling
- Programmable de-gamma curve
- Bezel adjustment
- Horizontal and vertical image flip
- DMD
interface:
- 78-MHz DDR DMD interface
- Consistent DMD data loading and reset control overtemperature operating range
- Automatic DMD parking at power-down
- DMD temperature management
- External
memory
support
- DDR2: 312-MHz clock (624-MHz data rate)
- Serial flash 39-MHz clock
- System
control
- I2C communication interface
- Programmable splash screens
- DMD power and reset driver control
- Programmable flash-based configuration
- Test
support
- Built-in test pattern generator
- JTAG with boundary scan support
- Packaged in a 216-pin, 1.0-mm pitch BGA
Description for the DLPC120-Q1
The DLPC120-Q1 DMD display controller for automotive applications is part of a chipset compatible with one of three digital micromirror devices (DMDs), DLP3030-Q1, DLP3020-Q1, or DLP3021-Q1. The core DLPC120-Q1 logic is responsible for accepting video input and formatting the data to display on the DMD while simultaneously controlling RGB LEDs in order to create a real-time image. The DLPC120-Q1 is also responsible for controlling the power-up and power-down events of the DMD, based on external system control or temperature input from the DMD. Combined with an external dimming circuit and microcontroller, the DLPC120-Q1 supports a wide dimming range > 5000:1 for HUD applications. Typically, the DLPC120-Q1 is a peripheral device in an I2C interface with a host processor.