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DP83TC818S-Q1

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Automotive 100BASE-T1 Ethernet PHY with MACsec, advanced TSN with AVB features, and TC-10

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Data sheet

DP83TC818S-Q1

ACTIVE
Data sheet Order now

Product details

Datarate (Mbps) 100BASE-T1 Interface type MII, RGMII, RMII, SGMII Number of ports Single Rating Automotive Features 25-MHz clock out, Cable diagnostics, IEEE 1588v2/802.1AS time synchronization and AVB clock generation, IEEE 802.1AE MACsec, IEEE 802.3bw & Open Alliance (OA) compliant, Integrated LPF, Single supply, TC10, Wettable flank package I/O supply voltage (typ) (V) 1.8, 2.5, 3.3 Operating temperature range (°C) -40 to 125 Number of LEDs 2 ESD HBM (kV) 8
Datarate (Mbps) 100BASE-T1 Interface type MII, RGMII, RMII, SGMII Number of ports Single Rating Automotive Features 25-MHz clock out, Cable diagnostics, IEEE 1588v2/802.1AS time synchronization and AVB clock generation, IEEE 802.1AE MACsec, IEEE 802.3bw & Open Alliance (OA) compliant, Integrated LPF, Single supply, TC10, Wettable flank package I/O supply voltage (typ) (V) 1.8, 2.5, 3.3 Operating temperature range (°C) -40 to 125 Number of LEDs 2 ESD HBM (kV) 8
VQFN (RHA) 36 36 mm² 6 x 6
  • Synchronized Audio Clock Generation
    • I2S & TDMx SCLK/FSYNC clock generation
    • Configurable FSYNC, SCLK, MCLK frequencies
    • Automatic Phase Adjustment through IEEE1722 CRF decode
  • IEEE 802.1AE MACsec
    • MACsec frame expansion: Inbuilt buffering and flow control support to handle 12 byte IPG ethernet frames
    • Authentication, encryption at line rate
    • Cipher suites: GCM-AES-XPN-128/256, GCM-AES-128/256
    • Secure Channel: Total 16 SAK enabling 8 Tx/Rx SC with SAK Auto rollover support
    • Ingress/Egress classification for Ethertype, VLAN, DMAC: up to 8 parallel rules
    • Window replay protection
  • IEEE 802.1AS time synchronization
    • Highly accurate 1pps signal < ±15 ns
    • Precise time stamping for MACsec encoded PTP packets
    • Multiple IOs for event capture and trigger
  • Robust EMC Performance
    • IEC62228-5, OA EMC compliant
    • SAE J2962-3 EMC compliant
    • 39dBm DPI Immunity with ±5% assymetry
    • <4dBµV radiated emissions in GPS and Glonass bands
    • Stripline Emissions: Class-II compliant
  • TC-10 compliant
    • < 18µA sleep current
    • Fast wake from sleep by retaining PHY configuration during sleep (optional)
  • MAC Interfaces: MII, RMII Master, RGMII, SGMII
  • Footprint compatible with TI’s 1000BASE-T1 PHY
    • Single board design for 100BASE-T1 and 1000BASE-T1 with required BOM change
  • Diagnostic tool kit
    • Signal Quality Indication (SQI) & Time Domain Reflectometry (TDR)
    • Voltage, Temperature & ESD sensors
    • PPM monitor: Provides external clock ppm drift (up to ±100 ppb accuracy)
  • AEC-Q100 qualified for Automotive Applications:
    • Temperature Grade 1: –40°C to +125 °C
    • IEC61000-4-2 ESD level 4 MDI: ±8kV CD
  • Synchronized Audio Clock Generation
    • I2S & TDMx SCLK/FSYNC clock generation
    • Configurable FSYNC, SCLK, MCLK frequencies
    • Automatic Phase Adjustment through IEEE1722 CRF decode
  • IEEE 802.1AE MACsec
    • MACsec frame expansion: Inbuilt buffering and flow control support to handle 12 byte IPG ethernet frames
    • Authentication, encryption at line rate
    • Cipher suites: GCM-AES-XPN-128/256, GCM-AES-128/256
    • Secure Channel: Total 16 SAK enabling 8 Tx/Rx SC with SAK Auto rollover support
    • Ingress/Egress classification for Ethertype, VLAN, DMAC: up to 8 parallel rules
    • Window replay protection
  • IEEE 802.1AS time synchronization
    • Highly accurate 1pps signal < ±15 ns
    • Precise time stamping for MACsec encoded PTP packets
    • Multiple IOs for event capture and trigger
  • Robust EMC Performance
    • IEC62228-5, OA EMC compliant
    • SAE J2962-3 EMC compliant
    • 39dBm DPI Immunity with ±5% assymetry
    • <4dBµV radiated emissions in GPS and Glonass bands
    • Stripline Emissions: Class-II compliant
  • TC-10 compliant
    • < 18µA sleep current
    • Fast wake from sleep by retaining PHY configuration during sleep (optional)
  • MAC Interfaces: MII, RMII Master, RGMII, SGMII
  • Footprint compatible with TI’s 1000BASE-T1 PHY
    • Single board design for 100BASE-T1 and 1000BASE-T1 with required BOM change
  • Diagnostic tool kit
    • Signal Quality Indication (SQI) & Time Domain Reflectometry (TDR)
    • Voltage, Temperature & ESD sensors
    • PPM monitor: Provides external clock ppm drift (up to ±100 ppb accuracy)
  • AEC-Q100 qualified for Automotive Applications:
    • Temperature Grade 1: –40°C to +125 °C
    • IEC61000-4-2 ESD level 4 MDI: ±8kV CD

The DP83TC818S-Q1 is an IEEE 802.3bw and Open Alliance (OA) compliant automotive qualified 100Base-T1 Ethernet physical layer transceiver. The device provides all physical layer functions needed to transmit and receive data over unshielded/shielded single twisted-pair cables with xMII interface flexibility and TC10 Sleep-Wake functionality.

The DP83TC818S-Q1 integrates IEEE802.1AS / IEEE1588v2 hardware time stamping & fractional PLL, enabling highly accurate time synchronization. The fractional PLL enables frequency and phase synchronization of the wall clock (eliminating the need for external VCXO) and generation of a wide range of time synchronized frequencies needed for audio and other ADAS applications. The PHY also integrates IEEE 1722 CRF decode to generate Media clock and Bit Clock for AVB & other audio applications.

The DP83TC818S-Q1 integrates IEEE 802.1AE line rate security with authentication and optional encryption support to secure communication over the network. The DP83TC818S-Q1 supports up to 16 secure association (SA) channels with automatic SAK rollover and extended packet numbering support. DP83TC818S-Q1 offers ingress classification to filter the unwanted packets & supports WAN MACsec for end-to-end security.

The DP83TC818S-Q1 is footprint compatible to TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs enabling design scalability with a single board for different speeds and features.

The DP83TC818S-Q1 is an IEEE 802.3bw and Open Alliance (OA) compliant automotive qualified 100Base-T1 Ethernet physical layer transceiver. The device provides all physical layer functions needed to transmit and receive data over unshielded/shielded single twisted-pair cables with xMII interface flexibility and TC10 Sleep-Wake functionality.

The DP83TC818S-Q1 integrates IEEE802.1AS / IEEE1588v2 hardware time stamping & fractional PLL, enabling highly accurate time synchronization. The fractional PLL enables frequency and phase synchronization of the wall clock (eliminating the need for external VCXO) and generation of a wide range of time synchronized frequencies needed for audio and other ADAS applications. The PHY also integrates IEEE 1722 CRF decode to generate Media clock and Bit Clock for AVB & other audio applications.

The DP83TC818S-Q1 integrates IEEE 802.1AE line rate security with authentication and optional encryption support to secure communication over the network. The DP83TC818S-Q1 supports up to 16 secure association (SA) channels with automatic SAK rollover and extended packet numbering support. DP83TC818S-Q1 offers ingress classification to filter the unwanted packets & supports WAN MACsec for end-to-end security.

The DP83TC818S-Q1 is footprint compatible to TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs enabling design scalability with a single board for different speeds and features.
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* Data sheet DP83TC818S-Q1 Precise and Secure 100BASE-T1 Automotive Ethernet with AVB Clock Generation, IEEE802.1AE MACsec, IEEE802.1AS and TC10 Sleep-Wake datasheet (Rev. A) PDF | HTML 19 Nov 2024
Application note SGMII Troubleshooting Guide PDF | HTML 05 Nov 2024

Design & development

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Evaluation board

DP83TC818EVM-MC — DP83TC818S-Q1 evaluation model

The DP83TC818EVM-MC supports 100 Mbps speed and is IEEE 802.3bp compliant. There is an on-board MSP430F5529 for use with the USB2MDIO graphical user interface tool. The DP83867 is provided for copper (100BASE-TX) support using the RGMII MAC Interface.

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Reference designs

TIDA-020071 — TDA4 quad-automotive PHY RGMII reference design

This reference design interfaces with Jacinto™ 7 processor EVM boards through the RGMII Ethernet Expansion Connector. Four automotive Ethernet connections are added through TI's automotive Ethernet physical layers (PHY). This design shows an implementation with TI's DP83TC818S-Q1 100Mbps and (...)
Design guide: PDF
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