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These 8-bit positive-edge-triggered D-type flip-flops with a clock (CLK) input are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators.
Data (D) input information that meets the setup time requirements
is transferred to the Q outputs on the positive-going edge of the
clock pulse if the common clock-enable (
) input is low. Clock triggering
occurs at a particular voltage level and is not directly related to
the transition time of the positive-going pulse. When the buffered
clock (CLK) input is at either the high or low level, the D-input
signal has no effect at the output. The circuits are designed to
prevent false clocking by transitions at .
The SN54ABT377 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT377A is characterized for operation from -40°C to 85°C.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | Octal Edge-Triggered D-Type Flip-Flops With Clock Enable datasheet (Rev. E) | 01 Jan 1997 |
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