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SN54AHCT138

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3-Line To 8-Line Decoders/Demultiplexers

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Data sheet

SN54AHCT138

ACTIVE
Data sheet Order now

Product details

Technology family AHCT Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Military Supply current (max) (µA) 40
Technology family AHCT Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Military Supply current (max) (µA) 40
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 CFP (W) 16 69.319 mm² 10.3 x 6.73 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Inputs are TTL-voltage compatible
  • Designed specifically for high-speed memory decoders and data-transmission systems
  • Incorporate three enable inputs to simplify cascading and/or data reception
  • Latch-up performance exceeds 250mA per JESD 17
  • ESD protection exceeds JESD 22
    • ±2000V human-body model (A114-A)
    • ±1000V charged-device model (C101)
  • Inputs are TTL-voltage compatible
  • Designed specifically for high-speed memory decoders and data-transmission systems
  • Incorporate three enable inputs to simplify cascading and/or data reception
  • Latch-up performance exceeds 250mA per JESD 17
  • ESD protection exceeds JESD 22
    • ±2000V human-body model (A114-A)
    • ±1000V charged-device model (C101)

The ’AHCT138 3-line to 8-line decoders/demultiplexers are designed to be used in high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding.

The ’AHCT138 3-line to 8-line decoders/demultiplexers are designed to be used in high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding.

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Technical documentation

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Type Title Date
* Data sheet SNx4AHCT138 3-Line to 8-Line Decoders/Demultiplexers datasheet (Rev. O) PDF | HTML 12 Jul 2024
* SMD SN54AHCT138 SMD 5962-98517 21 Jun 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
Product overview Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Live Insertion 01 Oct 1996

Design & development

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Package Pins CAD symbols, footprints & 3D models
CDIP (J) 16 Ultra Librarian
CFP (W) 16 Ultra Librarian
LCCC (FK) 20 Ultra Librarian
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