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D-type flip-flops

SN54HC175

ACTIVE

Quadruple D-type Flip-Flops With Clear

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Data sheet

SN54HC175

ACTIVE
Data sheet Order now

Product details

Number of channels 4 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 25 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 80 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 4 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 25 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 80 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 CFP (W) 16 69.319 mm² 10.3 x 6.73 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Wide operating voltage range of 2 V to 6 V
  • Outputs can drive up to 10 LSTTL Loads
  • Low power consumption, 80-µA max ICC
  • Contain four flip-flops with double-rail outputs
  • Typical tpd = 13 ns
  • ±4-mA output drive at 5 V
  • Low input current of 1 µA max
  • Wide operating voltage range of 2 V to 6 V
  • Outputs can drive up to 10 LSTTL Loads
  • Low power consumption, 80-µA max ICC
  • Contain four flip-flops with double-rail outputs
  • Typical tpd = 13 ns
  • ±4-mA output drive at 5 V
  • Low input current of 1 µA max

These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. The ’HC175 devices feature complementary outputs from each flip-flop.

These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. The ’HC175 devices feature complementary outputs from each flip-flop.
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Technical documentation

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Type Title Date
* Data sheet SNx4HC175 Quadruple D-Type Flip-Flops With Clear datasheet (Rev. F) PDF | HTML 24 Jun 2022
* SMD SN54HC175 SMD 84089012A 21 Jun 2016
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Package Pins CAD symbols, footprints & 3D models
CDIP (J) 16 Ultra Librarian
CFP (W) 16 Ultra Librarian
LCCC (FK) 20 Ultra Librarian
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