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SN54SC4T125-SEP

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Radiation-tolerant four-bit fixed-direction level translator

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Data sheet

SN54SC4T125-SEP

ACTIVE
Data sheet Order now

Product details

Technology family SCxT Applications GPIO Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 0 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -16 IOL (max) (mA) -16 Supply current (max) (µA) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type TTL-Compatible CMOS Output type 3-State Rating Space Operating temperature range (°C) -55 to 125
Technology family SCxT Applications GPIO Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 0 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -16 IOL (max) (mA) -16 Supply current (max) (µA) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type TTL-Compatible CMOS Output type 3-State Rating Space Operating temperature range (°C) -55 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4

  • VID V62/23631-01XE

  • Radiation Tolerant

    • Single Event Latch-Up (SEL) immune up to 43 MeV-cm 2/mg at 125°C

    • Total Ionizing Does (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30 krad(Si)

    • Single Event Transient (SET) characterized up to LET = 43 MeV-cm 2/mg

  • Wide operating range of 1.2 V to 5.5 V

  • Single-supply voltage translator:

    • Up translation:

      • 1.2 V to 1.8 V

      • 1.5 V to 2.5 V

      • 1.8 V to 3.3 V

      • 3.3 V to 5.0 V

    • Down translation:

      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150 Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17

  • Space Enhanced Plastic

    • Controlled baseline

    • Au bondwire and NiPdAu lead finish

    • Meets NASA ASTM E595 outgassing specification

    • One fabrication, assembly, and test site

    • Extended product life cycle

    • Product traceability

  • VID V62/23631-01XE

  • Radiation Tolerant

    • Single Event Latch-Up (SEL) immune up to 43 MeV-cm 2/mg at 125°C

    • Total Ionizing Does (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30 krad(Si)

    • Single Event Transient (SET) characterized up to LET = 43 MeV-cm 2/mg

  • Wide operating range of 1.2 V to 5.5 V

  • Single-supply voltage translator:

    • Up translation:

      • 1.2 V to 1.8 V

      • 1.5 V to 2.5 V

      • 1.8 V to 3.3 V

      • 3.3 V to 5.0 V

    • Down translation:

      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150 Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17

  • Space Enhanced Plastic

    • Controlled baseline

    • Au bondwire and NiPdAu lead finish

    • Meets NASA ASTM E595 outgassing specification

    • One fabrication, assembly, and test site

    • Extended product life cycle

    • Product traceability

The SN54SC4T125-SEP contains four independent buffers with 3-state outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be put into a high impedance (Hi-Z) state by applying a HIGH on the OE pin. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The SN54SC4T125-SEP contains four independent buffers with 3-state outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be put into a high impedance (Hi-Z) state by applying a HIGH on the OE pin. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
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Technical documentation

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Type Title Date
* Data sheet SN54SC4T125-SEP Radiation Tolerant, Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter datasheet PDF | HTML 15 Nov 2023
* Radiation & reliability report SN54SC4T125-SEP Single Event Effects Report PDF | HTML 05 Dec 2023
* Radiation & reliability report SN54SC4T125-SEP Total Ionizing Dose (TID) Report PDF | HTML 01 Dec 2023
* Radiation & reliability report SN54SC4T125-SEP Production Flow and Reliability Report PDF | HTML 09 Nov 2023
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02 Oct 2024
Application brief TI Space Enhanced Plastic Logic Overview and Applications in Low-Earth Orbit Satellite Platforms PDF | HTML 10 Sep 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 Jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 Jul 2024

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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TSSOP (PW) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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